diff options
author | Peng Fan <peng.fan@nxp.com> | 2024-09-24 15:31:59 +0800 |
---|---|---|
committer | Fabio Estevam <festevam@gmail.com> | 2024-09-24 16:55:14 -0300 |
commit | 94d02f13dbc582cf0644a53da33cc4ad9213661f (patch) | |
tree | 96778bc2e7f500100936d7b4ef8f6a61b7e3825e | |
parent | be847fafa71deaa3d11707c3a193a4a52f34b05d (diff) |
net: fec_mxc: Fix clk_ref rate on iMX93
i.MX93 FEC ENET port supports two mode: RGMII and RMII. For RGMII,
there is an internal /2 divider, so the freq needs to set with (*2),
otherwise the speed will not reach 1G and cause communication error
in some network environments. For RMII, the clk path is
ccm -> enet tx_clk pin -> pad loop back to enet, no /2 divider.
So fix for RGMII mode with freq multiplied by 2.
Fixes: 09de565f76b ("net: fec_mxc: support i.MX93")
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
-rw-r--r-- | drivers/net/fec_mxc.c | 7 |
1 files changed, 5 insertions, 2 deletions
diff --git a/drivers/net/fec_mxc.c b/drivers/net/fec_mxc.c index 0a0d92bc2cd..d0590fd137b 100644 --- a/drivers/net/fec_mxc.c +++ b/drivers/net/fec_mxc.c @@ -1210,10 +1210,13 @@ static int fecmxc_set_ref_clk(struct clk *clk_ref, phy_interface_t interface) else if (interface == PHY_INTERFACE_MODE_RGMII || interface == PHY_INTERFACE_MODE_RGMII_ID || interface == PHY_INTERFACE_MODE_RGMII_RXID || - interface == PHY_INTERFACE_MODE_RGMII_TXID) + interface == PHY_INTERFACE_MODE_RGMII_TXID) { freq = 125000000; - else + if (is_imx93()) + freq = freq << 1; + } else { return -EINVAL; + } ret = clk_set_rate(clk_ref, freq); if (ret < 0) |