diff options
| author | Yao Zi <ziyao@disroot.org> | 2025-05-13 09:04:58 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2025-05-21 16:49:52 +0800 |
| commit | 976b90f9dac27a2d29064f23cfc3b3cd12417bc8 (patch) | |
| tree | f63511693f015c7fd3bb1f3ab510d0bb0a70a109 | |
| parent | 05240d541a407fbb62eec43f40a2b831bb1c1fe0 (diff) | |
riscv: dts: th1520: Preserve necessary devices for SPL
SPL for TH1520 requires CPU and boot UART nodes to function. Preserve
them in SPL devicetree blob with bootph-pre-ram property.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/dts/th1520.dtsi | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index cbe3481fadd..b34ac323503 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -14,6 +14,7 @@ cpus: cpus { #address-cells = <1>; #size-cells = <0>; + bootph-pre-ram; timebase-frequency = <3000000>; c910_0: cpu@0 { @@ -21,6 +22,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <0>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -42,6 +44,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <1>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -63,6 +66,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <2>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -84,6 +88,7 @@ device_type = "cpu"; riscv,isa = "rv64imafdc"; reg = <3>; + bootph-pre-ram; i-cache-block-size = <64>; i-cache-size = <65536>; i-cache-sets = <512>; @@ -173,6 +178,7 @@ uart0: serial@ffe7014000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xe7014000 0x0 0x100>; + bootph-pre-ram; interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; clocks = <&uart_sclk>; reg-shift = <2>; |