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authorYao Zi <ziyao@disroot.org>2025-06-06 04:28:04 +0000
committerLeo Yu-Chi Liang <ycliang@andestech.com>2025-07-03 16:14:13 +0800
commita23c1b3fc09431a2787c0ff5f9b3aea5c754ad6d (patch)
treebf2526037839e983e358af571c0646f306a53220
parentddb52eac41c83940b76db24b49ef3112f4c6549f (diff)
board: thead: licheepi4a: Bring up secondary cores in SPL
Setup core information and bring secondary HARTs up for a functional multi-core system. Signed-off-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
-rw-r--r--board/thead/th1520_lpi4a/spl.c3
1 files changed, 3 insertions, 0 deletions
diff --git a/board/thead/th1520_lpi4a/spl.c b/board/thead/th1520_lpi4a/spl.c
index 25dfa387c36..d75fa6f3eff 100644
--- a/board/thead/th1520_lpi4a/spl.c
+++ b/board/thead/th1520_lpi4a/spl.c
@@ -39,6 +39,9 @@ void board_init_f(ulong dummy)
if (ret)
panic("failed to bind CPU: %d\n", ret);
+ riscv_cpu_setup();
+ th1520_kick_secondary_cores();
+
spl_dram_init();
icache_enable();