diff options
| author | Yao Zi <ziyao@disroot.org> | 2025-06-18 09:54:56 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2025-07-03 18:10:58 +0800 |
| commit | a4f9013e311de2095148ce3dbe9dadaae812e51b (patch) | |
| tree | 212b2793fd0c32b6279ad0d23748d010054e5f48 | |
| parent | 4981db81303b68de3ff1e2278e1d95a6534039d3 (diff) | |
riscv: dts: th1520: Add pin controllers
Describe the three pin controllers integrated in TH1520 SoC. Since we
don't have support for clocks in the AON region, a dummy fixed-clock
node is added to supply the pin controller locating in it.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Acked-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/dts/th1520.dtsi | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index e773d2e6a80..8306eda5521 100644 --- a/arch/riscv/dts/th1520.dtsi +++ b/arch/riscv/dts/th1520.dtsi @@ -128,6 +128,13 @@ #clock-cells = <0>; }; + aonsys_clk: clock-73728000 { + compatible = "fixed-clock"; + clock-frequency = <73728000>; + clock-output-names = "aonsys_clk"; + #clock-cells = <0>; + }; + soc { compatible = "simple-bus"; interrupt-parent = <&plic>; @@ -259,6 +266,13 @@ }; }; + padctrl1_apsys: pinctrl@ffe7f3c000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xe7f3c000 0x0 0x1000>; + clocks = <&clk CLK_PADCTRL1>; + thead,pad-group = <2>; + }; + gpio0: gpio@ffec005000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xec005000 0x0 0x1000>; @@ -299,6 +313,13 @@ }; }; + padctrl0_apsys: pinctrl@ffec007000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xec007000 0x0 0x1000>; + clocks = <&clk CLK_PADCTRL0>; + thead,pad-group = <3>; + }; + uart2: serial@ffec010000 { compatible = "snps,dw-apb-uart"; reg = <0xff 0xec010000 0x0 0x4000>; @@ -439,6 +460,13 @@ }; }; + padctrl_aosys: pinctrl@fffff4a000 { + compatible = "thead,th1520-pinctrl"; + reg = <0xff 0xfff4a000 0x0 0x2000>; + clocks = <&aonsys_clk>; + thead,pad-group = <1>; + }; + ao_gpio1: gpio@fffff52000 { compatible = "snps,dw-apb-gpio"; reg = <0xff 0xfff52000 0x0 0x1000>; |