Merge branch '2022-07-25-assorted-platform-updates'

- Assorted TI, Apple, Snapdragon and Xen updates.

103 files changed, 1861 insertions, 230 deletions

diff --git a/MAINTAINERS b/MAINTAINERS
index cd54e6663d0..31291d34f35 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1364,6 +1364,7 @@ F:	arch/arm/mach-k3/config_secure.mk
 F:	configs/am335x_hs_evm_defconfig
 F:	configs/am335x_hs_evm_uart_defconfig
 F:	configs/am43xx_hs_evm_defconfig
+F:	configs/am43xx_hs_evm_qspi_defconfig
 F:	configs/am57xx_hs_evm_defconfig
 F:	configs/am57xx_hs_evm_usb_defconfig
 F:	configs/dra7xx_hs_evm_defconfig
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d4fc83318a6..0d4903a2eb5 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -2149,21 +2149,6 @@ config TI_SECURE_DEVICE
 	  authenticated) and the code. See the doc/README.ti-secure
 	  file for further details.
 
-if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
-config ISW_ENTRY_ADDR
-	hex "Address in memory or XIP address of bootloader entry point"
-	default 0x402F4000 if AM43XX
-	default 0x402F0400 if AM33XX
-	default 0x40301350 if OMAP54XX
-	help
-	  After any reset, the boot ROM searches the boot media for a valid
-	  boot image. For non-XIP devices, the ROM then copies the image into
-	  internal memory. For all boot modes, after the ROM processes the
-	  boot image it eventually computes the entry point address depending
-	  on the device type (secure/non-secure), boot media (xip/non-xip) and
-	  image headers.
-endif
-
 config SYS_KWD_CONFIG
 	string "kwbimage config file path"
 	depends on ARCH_KIRKWOOD || ARCH_MVEBU
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
index 42c7790ee8f..7fa275ea7cc 100644
--- a/arch/arm/dts/Makefile
+++ b/arch/arm/dts/Makefile
@@ -505,6 +505,7 @@ dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb
 dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb
 dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb
+dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb
 
 dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb
 
@@ -1193,7 +1194,7 @@ dtb-$(CONFIG_STM32MP15x) += \
 	stm32mp15xx-dhcor-avenger96.dtb \
 	stm32mp15xx-dhcor-drc-compact.dtb
 
-dtb-$(CONFIG_SOC_K3_AM6) += \
+dtb-$(CONFIG_SOC_K3_AM654) += \
 	k3-am654-base-board.dtb \
 	k3-am654-r5-base-board.dtb \
 	k3-am65-iot2050-spl.dtb \
diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts
index 7e56140df26..50523712cb3 100644
--- a/arch/arm/dts/dragonboard410c.dts
+++ b/arch/arm/dts/dragonboard410c.dts
@@ -137,9 +137,14 @@
 			};
 		};
 
-		spmi@200f000 {
+		spmi_bus: spmi@200f000 {
 			compatible = "qcom,spmi-pmic-arb";
-			reg = <0x200f800 0x200 0x2400000 0x400000 0x2c00000 0x400000>;
+			reg = <0x0200f000 0x001000>,
+			      <0x02400000 0x400000>,
+			      <0x02c00000 0x400000>,
+			      <0x03800000 0x200000>,
+			      <0x0200a000 0x002100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 			pmic0: pm8916@0 {
diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts
index 1114ddd7d3b..b72a2471cfa 100644
--- a/arch/arm/dts/dragonboard820c.dts
+++ b/arch/arm/dts/dragonboard820c.dts
@@ -93,11 +93,14 @@
 			clock-frequency = <200000000>;
 		 };
 
-		spmi@400f000 {
+		spmi_bus: spmi@400f000 {
 			compatible = "qcom,spmi-pmic-arb";
-			reg = <0x400f800 0x200>,
-			      <0x4400000 0x400000>,
-			      <0x4c00000 0x400000>;
+			reg = <0x0400f000 0x1000>,
+			      <0x04400000 0x800000>,
+			      <0x04c00000 0x800000>,
+			      <0x05800000 0x200000>,
+			      <0x0400a000 0x002100>;
+			reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
 			#address-cells = <0x1>;
 			#size-cells = <0x1>;
 
diff --git a/arch/arm/dts/dragonboard845c-uboot.dtsi b/arch/arm/dts/dragonboard845c-uboot.dtsi
new file mode 100644
index 00000000000..8b5a7ee573b
--- /dev/null
+++ b/arch/arm/dts/dragonboard845c-uboot.dtsi
@@ -0,0 +1,37 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle Qualcomm Robotics RB3 Development Platform
+ * (dragonboard845c) pins
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/
+{
+	soc {
+		u-boot,dm-pre-reloc;
+
+		serial@a84000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		clock-controller@100000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		pinctrl_north@3900000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
+
+&pm8998_pon {
+	key_vol_down {
+		gpios = <&pm8998_pon 1 0>;
+		label = "key_vol_down";
+	};
+	key_power {
+		gpios = <&pm8998_pon 0 0>;
+		label = "key_power";
+	};
+};
diff --git a/arch/arm/dts/dragonboard845c.dts b/arch/arm/dts/dragonboard845c.dts
new file mode 100644
index 00000000000..1722dce33ff
--- /dev/null
+++ b/arch/arm/dts/dragonboard845c.dts
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm Robotics RB3 Development (dragonboard845c) board device
+ * tree source
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "sdm845.dtsi"
+
+/ {
+	model = "Thundercomm Dragonboard 845c";
+	compatible = "thundercomm,db845c", "qcom,sdm845";
+	#address-cells = <2>;
+	#size-cells = <2>;
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &debug_uart;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0xfdfa0000>;
+	};
+
+	psci {
+		compatible = "arm,psci-1.0";
+		method = "smc";
+	};
+
+	soc: soc {
+		serial@a84000 {
+			status = "okay";
+		};
+	};
+};
+
+#include "dragonboard845c-uboot.dtsi"
diff --git a/arch/arm/dts/k3-am625-r5-sk.dts b/arch/arm/dts/k3-am625-r5-sk.dts
index 5aab858edd1..6d696e720de 100644
--- a/arch/arm/dts/k3-am625-r5-sk.dts
+++ b/arch/arm/dts/k3-am625-r5-sk.dts
@@ -79,6 +79,15 @@
 	ti,secure-host;
 };
 
+&cbass_mcu {
+	mcu_esm: esm@4100000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x0 0x4100000 0x0 0x1000>;
+		ti,esm-pins = <0>, <1>, <2>, <85>;
+		u-boot,dm-spl;
+	};
+};
+
 &cbass_main {
 	sa3_secproxy: secproxy@44880000 {
 		u-boot,dm-spl;
@@ -96,6 +105,13 @@
 		mbox-names = "tx", "rx", "boot_notify";
 		u-boot,dm-spl;
 	};
+
+	main_esm: esm@420000 {
+		compatible = "ti,j721e-esm";
+		reg = <0x0 0x420000 0x0 0x1000>;
+		ti,esm-pins = <160>, <161>, <162>, <163>, <177>, <178>;
+		u-boot,dm-spl;
+	};
 };
 
 &mcu_pmx0 {
diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi
index 8324b389e06..d6510935219 100644
--- a/arch/arm/dts/k3-am64-ddr.dtsi
+++ b/arch/arm/dts/k3-am64-ddr.dtsi
@@ -768,7 +768,6 @@
 			DDRSS_PI_319_DATA
 			DDRSS_PI_320_DATA
 			DDRSS_PI_321_DATA
-			DDRSS_PI_321_DATA
 			DDRSS_PI_322_DATA
 			DDRSS_PI_323_DATA
 			DDRSS_PI_324_DATA
diff --git a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
index 4f2f04851d1..2ac933a6ac9 100644
--- a/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
+++ b/arch/arm/dts/mt7622-bananapi-bpi-r64.dts
@@ -182,8 +182,6 @@
 };
 
 &uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/mt7622-rfb.dts b/arch/arm/dts/mt7622-rfb.dts
index c2f1ad2011a..30a91374070 100644
--- a/arch/arm/dts/mt7622-rfb.dts
+++ b/arch/arm/dts/mt7622-rfb.dts
@@ -189,8 +189,6 @@
 };
 
 &uart0 {
-	pinctrl-names = "default";
-	pinctrl-0 = <&uart0_pins>;
 	status = "okay";
 };
 
diff --git a/arch/arm/dts/qcs404-evb-uboot.dtsi b/arch/arm/dts/qcs404-evb-uboot.dtsi
new file mode 100644
index 00000000000..c18080a4834
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb-uboot.dtsi
@@ -0,0 +1,24 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * U-Boot addition to handle QCS404 EVB pre-relocation devices
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/ {
+	soc {
+		u-boot,dm-pre-reloc;
+
+		pinctrl_north@1300000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		clock-controller@1800000 {
+			u-boot,dm-pre-reloc;
+		};
+
+		serial@78b1000 {
+			u-boot,dm-pre-reloc;
+		};
+	};
+};
diff --git a/arch/arm/dts/qcs404-evb.dts b/arch/arm/dts/qcs404-evb.dts
new file mode 100644
index 00000000000..4f0ae20bdb3
--- /dev/null
+++ b/arch/arm/dts/qcs404-evb.dts
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 based evaluation board device tree source
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+/dts-v1/;
+
+#include "skeleton64.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/pinctrl-snapdragon.h>
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
+/ {
+	model = "Qualcomm Technologies, Inc. QCS404 EVB";
+	compatible = "qcom,qcs404-evb", "qcom,qcs404";
+	#address-cells = <0x2>;
+	#size-cells = <0x2>;
+
+	chosen {
+		stdout-path = "serial0:115200n8";
+	};
+
+	aliases {
+		serial0 = &debug_uart;
+	};
+
+	memory {
+		device_type = "memory";
+		reg = <0 0x80000000 0 0x40000000>;
+	};
+
+	soc {
+		#address-cells = <0x1>;
+		#size-cells = <0x1>;
+		ranges = <0x0 0x0 0x0 0xffffffff>;
+		compatible = "simple-bus";
+
+		pinctrl_north@1300000 {
+			compatible = "qcom,tlmm-qcs404";
+			reg = <0x1300000 0x200000>;
+
+			blsp1_uart2: uart {
+				pins = "GPIO_17", "GPIO_18";
+				function = "blsp_uart2";
+			};
+		};
+
+		gcc: clock-controller@1800000 {
+			compatible = "qcom,gcc-qcs404";
+			reg = <0x1800000 0x80000>;
+			#address-cells = <0x1>;
+			#size-cells = <0x0>;
+		};
+
+		debug_uart: serial@78b1000 {
+			compatible = "qcom,msm-uartdm-v1.4";
+			reg = <0x78b1000 0x200>;
+			clock = <&gcc GCC_BLSP1_UART2_APPS_CLK>,
+				<&gcc GCC_BLSP1_AHB_CLK>;
+			bit-rate = <0xFF>;
+			pinctrl-names = "uart";
+			pinctrl-0 = <&blsp1_uart2>;
+		};
+
+		sdhci@7804000 {
+			compatible = "qcom,sdhci-msm-v5";
+			reg = <0x7804000 0x1000 0x7805000 0x1000>;
+			clock = <&gcc GCC_SDCC1_APPS_CLK>,
+				<&gcc GCC_SDCC1_AHB_CLK>;
+			bus-width = <0x8>;
+			index = <0x0>;
+			non-removable;
+			mmc-ddr-1_8v;
+			mmc-hs400-1_8v;
+		};
+	};
+};
+
+#include "qcs404-evb-uboot.dtsi"
diff --git a/arch/arm/dts/sdm845.dtsi b/arch/arm/dts/sdm845.dtsi
index 6f2fb20d68b..df5b6dfcfc3 100644
--- a/arch/arm/dts/sdm845.dtsi
+++ b/arch/arm/dts/sdm845.dtsi
@@ -8,6 +8,7 @@
 
 /dts-v1/;
 
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
 #include "skeleton64.dtsi"
 
 / {
@@ -18,7 +19,6 @@
 		compatible = "simple-bus";
 
 		gcc: clock-controller@100000 {
-			u-boot,dm-pre-reloc;
 			compatible = "qcom,gcc-sdm845";
 			reg = <0x100000 0x1f0000>;
 			#clock-cells = <1>;
@@ -27,7 +27,6 @@
 		};
 
 		gpio_north: gpio_north@3900000 {
-			u-boot,dm-pre-reloc;
 			#gpio-cells = <2>;
 			compatible = "qcom,sdm845-pinctrl";
 			reg = <0x3900000 0x400000>;
@@ -38,7 +37,6 @@
 		};
 
 		tlmm_north: pinctrl_north@3900000 {
-			u-boot,dm-pre-reloc;
 			compatible = "qcom,tlmm-sdm845";
 			reg = <0x3900000 0x400000>;
 			gpio-count = <150>;
@@ -49,7 +47,7 @@
 			/* DEBUG UART */
 			qup_uart9: qup-uart9-default {
 				pins = "GPIO_4", "GPIO_5";
-				function = "gpio";
+				function = "qup9";
 			};
 		};
 
@@ -58,7 +56,7 @@
 			reg = <0xa84000 0x4000>;
 			reg-names = "se_phys";
 			clock-names = "se-clk";
-			clocks = <&gcc 0x58>;
+			clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>;
 			pinctrl-names = "default";
 			pinctrl-0 = <&qup_uart9>;
 			qcom,wrapper-core = <0x8a>;
diff --git a/arch/arm/dts/starqltechn-uboot.dtsi b/arch/arm/dts/starqltechn-uboot.dtsi
index b55cccfe141..8d5d09c3a50 100644
--- a/arch/arm/dts/starqltechn-uboot.dtsi
+++ b/arch/arm/dts/starqltechn-uboot.dtsi
@@ -16,16 +16,14 @@
 		serial@a84000 {
 			u-boot,dm-pre-reloc;
 		};
-		gcc {
-			clock-controller@100000 {
-				u-boot,dm-pre-reloc;
-			};
-			gpio_north@3900000 {
-				u-boot,dm-pre-reloc;
-			};
-			pinctrl@3900000 {
-				u-boot,dm-pre-reloc;
-			};
+		clock-controller@100000 {
+			u-boot,dm-pre-reloc;
+		};
+		gpio_north@3900000 {
+			u-boot,dm-pre-reloc;
+		};
+		pinctrl_north@3900000 {
+			u-boot,dm-pre-reloc;
 		};
 	};
 };
diff --git a/arch/arm/dts/starqltechn.dts b/arch/arm/dts/starqltechn.dts
index 0261388319e..34a4f59cbd1 100644
--- a/arch/arm/dts/starqltechn.dts
+++ b/arch/arm/dts/starqltechn.dts
@@ -48,7 +48,7 @@
 			status = "okay";
 		};
 
-		pinctrl@3900000 {
+		pinctrl_north@3900000 {
 			muic_i2c: muic_i2c {
 				pins = "GPIO_33", "GPIO_34";
 				drive-strength = <0x2>;
diff --git a/arch/arm/mach-apple/board.c b/arch/arm/mach-apple/board.c
index 1525a9edee8..16046423128 100644
--- a/arch/arm/mach-apple/board.c
+++ b/arch/arm/mach-apple/board.c
@@ -16,7 +16,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-/* Apple M1 */
+/* Apple M1/M2 */
 
 static struct mm_region t8103_mem_map[] = {
 	{
@@ -376,7 +376,8 @@ void build_mem_map(void)
 	fdt_size_t size;
 	int i;
 
-	if (of_machine_is_compatible("apple,t8103"))
+	if (of_machine_is_compatible("apple,t8103") ||
+	    of_machine_is_compatible("apple,t8112"))
 		mem_map = t8103_mem_map;
 	else if (of_machine_is_compatible("apple,t6000"))
 		mem_map = t6000_mem_map;
diff --git a/arch/arm/mach-davinci/Makefile b/arch/arm/mach-davinci/Makefile
index ed882740720..ae171e3ee22 100644
--- a/arch/arm/mach-davinci/Makefile
+++ b/arch/arm/mach-davinci/Makefile
@@ -7,14 +7,9 @@
 
 obj-y				+= cpu.o misc.o timer.o psc.o pinmux.o reset.o
 obj-$(CONFIG_DA850_LOWLEVEL)	+= da850_lowlevel.o
-obj-$(CONFIG_SOC_DM355)	+= dm355.o
-obj-$(CONFIG_SOC_DM365)	+= dm365.o
-obj-$(CONFIG_SOC_DM644X)	+= dm644x.o
-obj-$(CONFIG_SOC_DM646X)	+= dm646x.o
 obj-$(CONFIG_SOC_DA850)	+= da850_pinmux.o
 
 ifdef CONFIG_SPL_BUILD
 obj-$(CONFIG_SPL_FRAMEWORK)	+= spl.o
-obj-$(CONFIG_SOC_DM365)	+= dm365_lowlevel.o
 obj-$(CONFIG_SOC_DA8XX)	+= da850_lowlevel.o
 endif
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 57f693e9a12..171a7f2f25f 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -4,8 +4,8 @@ choice
 	prompt "Texas Instruments' K3 based SoC select"
 	optional
 
-config SOC_K3_AM6
-	bool "TI's K3 based AM6 SoC Family Support"
+config SOC_K3_AM654
+	bool "TI's K3 based AM654 SoC Family Support"
 
 config SOC_K3_J721E
 	bool "TI's K3 based J721E SoC Family Support"
@@ -26,7 +26,7 @@ config SYS_SOC
 
 config SYS_K3_NON_SECURE_MSRAM_SIZE
 	hex
-	default 0x80000 if SOC_K3_AM6
+	default 0x80000 if SOC_K3_AM654
 	default 0x100000 if SOC_K3_J721E || SOC_K3_J721S2
 	default 0x1c0000 if SOC_K3_AM642
 	default 0x3c000 if SOC_K3_AM625
@@ -38,7 +38,7 @@ config SYS_K3_NON_SECURE_MSRAM_SIZE
 
 config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 	hex
-	default 0x58000 if SOC_K3_AM6
+	default 0x58000 if SOC_K3_AM654
 	default 0xc0000 if SOC_K3_J721E || SOC_K3_J721S2
 	default 0x180000 if SOC_K3_AM642
 	default 0x38000 if SOC_K3_AM625
@@ -48,21 +48,21 @@ config SYS_K3_MAX_DOWNLODABLE_IMAGE_SIZE
 
 config SYS_K3_MCU_SCRATCHPAD_BASE
 	hex
-	default 0x40280000 if SOC_K3_AM6
+	default 0x40280000 if SOC_K3_AM654
 	default 0x40280000 if SOC_K3_J721E || SOC_K3_J721S2
 	help
 	  Describes the base address of MCU Scratchpad RAM.
 
 config SYS_K3_MCU_SCRATCHPAD_SIZE
 	hex
-	default 0x200 if SOC_K3_AM6
+	default 0x200 if SOC_K3_AM654
 	default 0x200 if SOC_K3_J721E || SOC_K3_J721S2
 	help
 	  Describes the size of MCU Scratchpad RAM.
 
 config SYS_K3_BOOT_PARAM_TABLE_INDEX
 	hex
-	default 0x41c7fbfc if SOC_K3_AM6
+	default 0x41c7fbfc if SOC_K3_AM654
 	default 0x41cffbfc if SOC_K3_J721E
 	default 0x41cfdbfc if SOC_K3_J721S2
 	default 0x701bebfc if SOC_K3_AM642
@@ -176,6 +176,12 @@ config K3_DM_FW
 	  bootloader, it makes RM and PM services not being available
 	  during R5 SPL execution time.
 
+config K3_X509_SWRV
+	int "SWRV for X509 certificate used for boot images"
+	default 1
+	help
+	  SWRV for X509 certificate used for boot images
+
 source "board/ti/am65x/Kconfig"
 source "board/ti/am64x/Kconfig"
 source "board/ti/am62x/Kconfig"
diff --git a/arch/arm/mach-k3/Makefile b/arch/arm/mach-k3/Makefile
index 8459bef93bc..0dce8802dbb 100644
--- a/arch/arm/mach-k3/Makefile
+++ b/arch/arm/mach-k3/Makefile
@@ -3,16 +3,19 @@
 # Copyright (C) 2017-2018 Texas Instruments Incorporated - http://www.ti.com/
 #	Lokesh Vutla <lokeshvutla@ti.com>
 
-obj-$(CONFIG_SOC_K3_AM6) += am6_init.o
-obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o j721e/ j7200/
-obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o j721s2/
-obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
-obj-$(CONFIG_SOC_K3_AM625) += am625_init.o am62x/
+obj-$(CONFIG_SOC_K3_J721E) += j721e/ j7200/
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2/
+obj-$(CONFIG_SOC_K3_AM625) += am62x/
 obj-$(CONFIG_ARM64) += arm64-mmu.o
 obj-$(CONFIG_CPU_V7R) += r5_mpu.o lowlevel_init.o
 obj-$(CONFIG_TI_SECURE_DEVICE) += security.o
 obj-$(CONFIG_ARM64) += cache.o
 ifeq ($(CONFIG_SPL_BUILD),y)
+obj-$(CONFIG_SOC_K3_AM654) += am654_init.o
+obj-$(CONFIG_SOC_K3_J721E) += j721e_init.o
+obj-$(CONFIG_SOC_K3_J721S2) += j721s2_init.o
+obj-$(CONFIG_SOC_K3_AM642) += am642_init.o
+obj-$(CONFIG_SOC_K3_AM625) += am625_init.o
 obj-$(CONFIG_K3_LOAD_SYSFW) += sysfw-loader.o
 endif
 obj-y += common.o
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c
index 0d9525992bb..8c4b3491b14 100644
--- a/arch/arm/mach-k3/am625_init.c
+++ b/arch/arm/mach-k3/am625_init.c
@@ -15,8 +15,6 @@
 #include <dm/uclass-internal.h>
 #include <dm/pinctrl.h>
 
-#if defined(CONFIG_SPL_BUILD)
-
 /*
  * This uninitialized global variable would normal end up in the .bss section,
  * but the .bss is cleared between writing and reading this variable, so move
@@ -64,6 +62,15 @@ static void ctrl_mmr_unlock(void)
 	mmr_unlock(PADCFG_MMR1_BASE, 1);
 }
 
+static __maybe_unused void enable_mcu_esm_reset(void)
+{
+	/* Set CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RST_EN_Z  to '0' (low active) */
+	u32 stat = readl(CTRLMMR_MCU_RST_CTRL);
+
+	stat &= RST_CTRL_ESM_ERROR_RST_EN_Z_MASK;
+	writel(stat, CTRLMMR_MCU_RST_CTRL);
+}
+
 void board_init_f(ulong dummy)
 {
 	struct udevice *dev;
@@ -142,6 +149,20 @@ void board_init_f(ulong dummy)
 	/* Output System Firmware version info */
 	k3_sysfw_print_ver();
 
+	if (IS_ENABLED(CONFIG_ESM_K3)) {
+		/* Probe/configure ESM0 */
+		ret = uclass_get_device_by_name(UCLASS_MISC, "esm@420000", &dev);
+		if (ret)
+			printf("esm main init failed: %d\n", ret);
+
+		/* Probe/configure MCUESM */
+		ret = uclass_get_device_by_name(UCLASS_MISC, "esm@4100000", &dev);
+		if (ret)
+			printf("esm mcu init failed: %d\n", ret);
+
+		enable_mcu_esm_reset();
+	}
+
 #if defined(CONFIG_K3_AM64_DDRSS)
 	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
 	if (ret)
@@ -267,5 +288,3 @@ u32 spl_boot_device(void)
 
 	return bootmedia;
 }
-
-#endif /* CONFIG_SPL_BUILD */
diff --git a/arch/arm/mach-k3/am642_init.c b/arch/arm/mach-k3/am642_init.c
index b16de9c9f08..8428322ed9a 100644
--- a/arch/arm/mach-k3/am642_init.c
+++ b/arch/arm/mach-k3/am642_init.c
@@ -23,7 +23,6 @@
 #include <mmc.h>
 #include <dm/root.h>
 
-#if defined(CONFIG_SPL_BUILD)
 #define MCU_CTRL_MMR0_BASE			0x04500000
 #define CTRLMMR_MCU_RST_CTRL			0x04518170
 
@@ -348,7 +347,6 @@ u32 spl_boot_device(void)
 	else
 		return __get_backup_bootmedia(devstat);
 }
-#endif
 
 #if defined(CONFIG_SYS_K3_SPL_ATF)
 
diff --git a/arch/arm/mach-k3/am6_init.c b/arch/arm/mach-k3/am654_init.c
index 7992918adcd..768fdd69602 100644
--- a/arch/arm/mach-k3/am6_init.c
+++ b/arch/arm/mach-k3/am654_init.c
@@ -26,9 +26,7 @@
 
 DECLARE_GLOBAL_DATA_PTR;
 
-#ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_K3_LOAD_SYSFW
-#ifdef CONFIG_TI_SECURE_DEVICE
 struct fwl_data main_cbass_fwls[] = {
 	{ "MMCSD1_CFG", 2057, 1 },
 	{ "MMCSD0_CFG", 2058, 1 },
@@ -45,7 +43,6 @@ struct fwl_data main_cbass_fwls[] = {
 	{ "MCU_CPSW0", 1220, 1 },
 };
 #endif
-#endif
 
 static void ctrl_mmr_unlock(void)
 {
@@ -238,10 +235,8 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 	/* Disable ROM configured firewalls right after loading sysfw */
-#ifdef CONFIG_TI_SECURE_DEVICE
 	remove_fwl_configs(main_cbass_fwls, ARRAY_SIZE(main_cbass_fwls));
 	remove_fwl_configs(mcu_cbass_fwls, ARRAY_SIZE(mcu_cbass_fwls));
-#endif
 #else
 	/* Prepare console output */
 	preloader_console_init();
@@ -359,7 +354,6 @@ u32 spl_boot_device(void)
 	else
 		return __get_backup_bootmedia(devstat);
 }
-#endif
 
 #ifdef CONFIG_SYS_K3_SPL_ATF
 
diff --git a/arch/arm/mach-k3/arm64-mmu.c b/arch/arm/mach-k3/arm64-mmu.c
index 12cb89335ad..b4d7ab1f16d 100644
--- a/arch/arm/mach-k3/arm64-mmu.c
+++ b/arch/arm/mach-k3/arm64-mmu.c
@@ -13,7 +13,7 @@
 #include <asm/system.h>
 #include <asm/armv8/mmu.h>
 
-#ifdef CONFIG_SOC_K3_AM6
+#ifdef CONFIG_SOC_K3_AM654
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
 #define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 5)
 
@@ -64,7 +64,7 @@ struct mm_region am654_mem_map[NR_MMU_REGIONS] = {
 };
 
 struct mm_region *mem_map = am654_mem_map;
-#endif /* CONFIG_SOC_K3_AM6 */
+#endif /* CONFIG_SOC_K3_AM654 */
 
 #ifdef CONFIG_SOC_K3_J721E
 
@@ -222,7 +222,7 @@ struct mm_region *mem_map = j721s2_mem_map;
 
 #endif /* CONFIG_SOC_K3_J721S2 */
 
-#if (CONFIG_IS_ENABLED(SOC_K3_AM642) || CONFIG_IS_ENABLED(SOC_K3_AM625))
+#if defined(CONFIG_SOC_K3_AM642) || defined(CONFIG_SOC_K3_AM625)
 /* NR_DRAM_BANKS + 32bit IO + 64bit IO + terminator */
 #define NR_MMU_REGIONS	(CONFIG_NR_DRAM_BANKS + 3)
 
diff --git a/arch/arm/mach-k3/config.mk b/arch/arm/mach-k3/config.mk
index da458bcfb29..9306f2627d9 100644
--- a/arch/arm/mach-k3/config.mk
+++ b/arch/arm/mach-k3/config.mk
@@ -28,6 +28,17 @@ else
 KEY=$(patsubst "%",$(srctree)/%,$(CONFIG_SYS_K3_KEY))
 endif
 
+# X509 SWRV default
+SWRV = $(CONFIG_K3_X509_SWRV)
+# On HS use SECDEV provided software revision or warn if not available
+ifeq ($(CONFIG_TI_SECURE_DEVICE),y)
+ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/keys/swrv.txt),)
+SWRV= $(shell cat $(TI_SECURE_DEV_PKG)/keys/swrv.txt)
+else
+$(warning "WARNING: Software revision file not found. Default may not work on HS hardware.")
+endif
+endif
+
 # tiboot3.bin is mandated by ROM and ROM only supports R5 boot.
 # So restrict tiboot3.bin creation for CPU_V7R.
 ifdef CONFIG_CPU_V7R
@@ -42,7 +53,7 @@ image_check: $(obj)/u-boot-spl.bin FORCE
 
 tiboot3.bin: image_check FORCE
 	$(srctree)/tools/k3_gen_x509_cert.sh -c 16 -b $(obj)/u-boot-spl.bin \
-				-o $@ -l $(CONFIG_SPL_TEXT_BASE) -k $(KEY)
+				-o $@ -l $(CONFIG_SPL_TEXT_BASE) -r $(SWRV) -k $(KEY)
 
 INPUTS-y	+= tiboot3.bin
 endif
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h
index cfabd20cbd7..9118d052042 100644
--- a/arch/arm/mach-k3/include/mach/am62_hardware.h
+++ b/arch/arm/mach-k3/include/mach/am62_hardware.h
@@ -29,6 +29,7 @@
 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_SHIFT	10
 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_MASK	BIT(13)
 #define MAIN_DEVSTAT_BACKUP_BOOTMODE_CFG_SHIFT	13
+#define RST_CTRL_ESM_ERROR_RST_EN_Z_MASK	(~BIT(17))
 
 /* Primary Bootmode MMC Config macros */
 #define MAIN_DEVSTAT_PRIMARY_MMC_PORT_MASK	0x4
@@ -67,6 +68,8 @@
 #define MCU_CTRL_DEVICE_CLKOUT_32K_CTRL		(MCU_CTRL_MMR0_BASE + 0x8058)
 #define MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL	(0x3)
 
+#define CTRLMMR_MCU_RST_CTRL			(MCU_CTRL_MMR0_BASE + 0x18170)
+
 #define ROM_ENTENDED_BOOT_DATA_INFO		0x43c3f1e0
 
 /* Use Last 2K as Scratch pad */
diff --git a/arch/arm/mach-k3/include/mach/hardware.h b/arch/arm/mach-k3/include/mach/hardware.h
index 7c6928d5da1..7bbd5c22c98 100644
--- a/arch/arm/mach-k3/include/mach/hardware.h
+++ b/arch/arm/mach-k3/include/mach/hardware.h
@@ -6,7 +6,7 @@
 #ifndef _ASM_ARCH_HARDWARE_H_
 #define _ASM_ARCH_HARDWARE_H_
 
-#ifdef CONFIG_SOC_K3_AM6
+#ifdef CONFIG_SOC_K3_AM654
 #include "am6_hardware.h"
 #endif
 
diff --git a/arch/arm/mach-k3/include/mach/spl.h b/arch/arm/mach-k3/include/mach/spl.h
index 17996f2938b..c9a324a5f0f 100644
--- a/arch/arm/mach-k3/include/mach/spl.h
+++ b/arch/arm/mach-k3/include/mach/spl.h
@@ -6,7 +6,7 @@
 #ifndef _ASM_ARCH_SPL_H_
 #define _ASM_ARCH_SPL_H_
 
-#ifdef CONFIG_SOC_K3_AM6
+#ifdef CONFIG_SOC_K3_AM654
 #include "am6_spl.h"
 #endif
 
diff --git a/arch/arm/mach-k3/j721e_init.c b/arch/arm/mach-k3/j721e_init.c
index e56ca6d0f5f..1bea05aa513 100644
--- a/arch/arm/mach-k3/j721e_init.c
+++ b/arch/arm/mach-k3/j721e_init.c
@@ -24,9 +24,7 @@
 #include <mmc.h>
 #include <remoteproc.h>
 
-#ifdef CONFIG_SPL_BUILD
 #ifdef CONFIG_K3_LOAD_SYSFW
-#ifdef CONFIG_TI_SECURE_DEVICE
 struct fwl_data cbass_hc_cfg0_fwls[] = {
 	{ "PCIE0_CFG", 2560, 8 },
 	{ "PCIE1_CFG", 2561, 8 },
@@ -64,7 +62,6 @@ struct fwl_data cbass_hc_cfg0_fwls[] = {
 	{ "WKUP_CTRL_MMR0", 131, 16 },
 };
 #endif
-#endif
 
 static void ctrl_mmr_unlock(void)
 {
@@ -255,7 +252,6 @@ void board_init_f(ulong dummy)
 	preloader_console_init();
 
 	/* Disable ROM configured firewalls right after loading sysfw */
-#ifdef CONFIG_TI_SECURE_DEVICE
 	remove_fwl_configs(cbass_hc_cfg0_fwls, ARRAY_SIZE(cbass_hc_cfg0_fwls));
 	remove_fwl_configs(cbass_hc0_fwls, ARRAY_SIZE(cbass_hc0_fwls));
 	remove_fwl_configs(cbass_rc_cfg0_fwls, ARRAY_SIZE(cbass_rc_cfg0_fwls));
@@ -263,7 +259,6 @@ void board_init_f(ulong dummy)
 	remove_fwl_configs(infra_cbass0_fwls, ARRAY_SIZE(infra_cbass0_fwls));
 	remove_fwl_configs(mcu_cbass0_fwls, ARRAY_SIZE(mcu_cbass0_fwls));
 	remove_fwl_configs(wkup_cbass0_fwls, ARRAY_SIZE(wkup_cbass0_fwls));
-#endif
 #else
 	/* Prepare console output */
 	preloader_console_init();
@@ -384,7 +379,6 @@ u32 spl_boot_device(void)
 	else
 		return __get_backup_bootmedia(main_devstat);
 }
-#endif
 
 #ifdef CONFIG_SYS_K3_SPL_ATF
 
diff --git a/arch/arm/mach-k3/j721s2_init.c b/arch/arm/mach-k3/j721s2_init.c
index 2e64e44a80e..12da8136f9e 100644
--- a/arch/arm/mach-k3/j721s2_init.c
+++ b/arch/arm/mach-k3/j721s2_init.c
@@ -22,8 +22,6 @@
 #include <mmc.h>
 #include <remoteproc.h>
 
-#ifdef CONFIG_SPL_BUILD
-
 static void ctrl_mmr_unlock(void)
 {
 	/* Unlock all WKUP_CTRL_MMR0 module registers */
@@ -255,7 +253,6 @@ u32 spl_boot_device(void)
 	else
 		return __get_backup_bootmedia(main_devstat);
 }
-#endif
 
 #define J721S2_DEV_MCU_RTI0			295
 #define J721S2_DEV_MCU_RTI1			296
diff --git a/arch/arm/mach-omap2/config_secure.mk b/arch/arm/mach-omap2/config_secure.mk
index ebdc00fded3..0629afd0ee8 100644
--- a/arch/arm/mach-omap2/config_secure.mk
+++ b/arch/arm/mach-omap2/config_secure.mk
@@ -6,11 +6,11 @@ ifneq ($(TI_SECURE_DEV_PKG),)
 ifneq ($(wildcard $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh),)
 ifneq ($(CONFIG_SPL_BUILD),)
 cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
-	$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+	$(patsubst u-boot-spl_HS_%,%,$(@F)) $< $@ $(CONFIG_SPL_TEXT_BASE) \
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 else
 cmd_mkomapsecimg = $(TI_SECURE_DEV_PKG)/scripts/create-boot-image.sh \
-	$(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_ISW_ENTRY_ADDR) \
+	$(patsubst u-boot_HS_%,%,$(@F)) $< $@ $(CONFIG_SYS_TEXT_BASE) \
 	$(if $(KBUILD_VERBOSE:1=), >/dev/null)
 endif
 else
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 12cf02a56aa..09273333068 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -44,6 +44,19 @@ config TARGET_DRAGONBOARD820C
 	  - 3GiB RAM
 	  - 32GiB UFS drive
 
+config TARGET_DRAGONBOARD845C
+	bool "96Boards Dragonboard 845C"
+	help
+	  Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
+	  Platform. This board complies with 96Boards Open Platform
+	  Specifications. Features:
+	  - Qualcomm Snapdragon SDA845 SoC
+	  - 4GiB RAM
+	  - 64GiB UFS drive
+	select MISC_INIT_R
+	select SDM845
+	select DM_ETH if NET
+
 config TARGET_STARQLTECHN
 	bool "Samsung S9 SM-G9600(starqltechn)"
 	help
@@ -56,10 +69,22 @@ config TARGET_STARQLTECHN
 	select SDM845
 	select DM_ETH if NET
 
+config TARGET_QCS404EVB
+	bool "Qualcomm Technologies, Inc. QCS404 EVB"
+	select LINUX_KERNEL_IMAGE_HEADER
+	help
+	  Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
+	  Features:
+	  - Qualcomm Snapdragon QCS404 SoC
+	  - 1GiB RAM
+	  - 8GiB eMMC, uSD slot
+
 endchoice
 
 source "board/qualcomm/dragonboard410c/Kconfig"
 source "board/qualcomm/dragonboard820c/Kconfig"
+source "board/qualcomm/dragonboard845c/Kconfig"
 source "board/samsung/starqltechn/Kconfig"
+source "board/qualcomm/qcs404-evb/Kconfig"
 
 endif
diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile
index 962855eb8cc..0d31f10f68a 100644
--- a/arch/arm/mach-snapdragon/Makefile
+++ b/arch/arm/mach-snapdragon/Makefile
@@ -15,4 +15,7 @@ obj-y += dram.o
 obj-y += pinctrl-snapdragon.o
 obj-y += pinctrl-apq8016.o
 obj-y += pinctrl-apq8096.o
+obj-y += pinctrl-qcs404.o
 obj-$(CONFIG_SDM845) += pinctrl-sdm845.o
+obj-$(CONFIG_TARGET_QCS404EVB) += clock-qcs404.o
+obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o
diff --git a/arch/arm/mach-snapdragon/clock-qcs404.c b/arch/arm/mach-snapdragon/clock-qcs404.c
new file mode 100644
index 00000000000..bb8a6fe0677
--- /dev/null
+++ b/arch/arm/mach-snapdragon/clock-qcs404.c
@@ -0,0 +1,79 @@
+// SPDX-License-Identifier: BSD-3-Clause
+/*
+ * Clock drivers for Qualcomm QCS404
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <clk-uclass.h>
+#include <dm.h>
+#include <errno.h>
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include "clock-snapdragon.h"
+
+#include <dt-bindings/clock/qcom,gcc-qcs404.h>
+
+/* GPLL0 clock control registers */
+#define GPLL0_STATUS_ACTIVE BIT(31)
+
+static struct vote_clk gcc_blsp1_ahb_clk = {
+	.cbcr_reg = BLSP1_AHB_CBCR,
+	.ena_vote = APCS_CLOCK_BRANCH_ENA_VOTE,
+	.vote_bit = BIT(10) | BIT(5) | BIT(4),
+};
+
+static const struct bcr_regs uart2_regs = {
+	.cfg_rcgr = BLSP1_UART2_APPS_CFG_RCGR,
+	.cmd_rcgr = BLSP1_UART2_APPS_CMD_RCGR,
+	.M = BLSP1_UART2_APPS_M,
+	.N = BLSP1_UART2_APPS_N,
+	.D = BLSP1_UART2_APPS_D,
+};
+
+static const struct bcr_regs sdc_regs = {
+	.cfg_rcgr = SDCC_CFG_RCGR(1),
+	.cmd_rcgr = SDCC_CMD_RCGR(1),
+	.M = SDCC_M(1),
+	.N = SDCC_N(1),
+	.D = SDCC_D(1),
+};
+
+static struct pll_vote_clk gpll0_vote_clk = {
+	.status = GPLL0_STATUS,
+	.status_bit = GPLL0_STATUS_ACTIVE,
+	.ena_vote = APCS_GPLL_ENA_VOTE,
+	.vote_bit = BIT(0),
+};
+
+ulong msm_set_rate(struct clk *clk, ulong rate)
+{
+	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
+
+	switch (clk->id) {
+	case GCC_BLSP1_UART2_APPS_CLK:
+		/* UART: 115200 */
+		clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
+				     CFG_CLK_SRC_CXO);
+		clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
+		break;
+	case GCC_BLSP1_AHB_CLK:
+		clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
+		break;
+	case GCC_SDCC1_APPS_CLK:
+		/* SDCC1: 200MHz */
+		clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 4, 0, 0,
+				     CFG_CLK_SRC_GPLL0);
+		clk_enable_gpll0(priv->base, &gpll0_vote_clk);
+		clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
+		break;
+	case GCC_SDCC1_AHB_CLK:
+		clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
+		break;
+	default:
+		return 0;
+	}
+
+	return 0;
+}
diff --git a/arch/arm/mach-snapdragon/clock-sdm845.c b/arch/arm/mach-snapdragon/clock-sdm845.c
index 95726392388..f69be808983 100644
--- a/arch/arm/mach-snapdragon/clock-sdm845.c
+++ b/arch/arm/mach-snapdragon/clock-sdm845.c
@@ -14,6 +14,7 @@
 #include <errno.h>
 #include <asm/io.h>
 #include <linux/bitops.h>
+#include <dt-bindings/clock/qcom,gcc-sdm845.h>
 #include "clock-snapdragon.h"
 
 #define F(f, s, h, m, n) { (f), (s), (2 * (h) - 1), (m), (n) }
@@ -84,7 +85,7 @@ ulong msm_set_rate(struct clk *clk, ulong rate)
 	struct msm_clk_priv *priv = dev_get_priv(clk->dev);
 
 	switch (clk->id) {
-	case 0x58: /*UART2*/
+	case GCC_QUPV3_WRAP1_S1_CLK: /*UART2*/
 		return clk_init_uart(priv, rate);
 	default:
 		return 0;
diff --git a/arch/arm/mach-snapdragon/clock-snapdragon.c b/arch/arm/mach-snapdragon/clock-snapdragon.c
index 3deb08ac4a9..5652d2fa36e 100644
--- a/arch/arm/mach-snapdragon/clock-snapdragon.c
+++ b/arch/arm/mach-snapdragon/clock-snapdragon.c
@@ -136,6 +136,7 @@ static const struct udevice_id msm_clk_ids[] = {
 	{ .compatible = "qcom,gcc-msm8996" },
 	{ .compatible = "qcom,gcc-apq8096" },
 	{ .compatible = "qcom,gcc-sdm845" },
+	{ .compatible = "qcom,gcc-qcs404" },
 	{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
new file mode 100644
index 00000000000..4dc96b9fbc3
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-qcs404.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Qualcomm QCS404 sysmap
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+#ifndef _MACH_SYSMAP_QCS404_H
+#define _MACH_SYSMAP_QCS404_H
+
+#define GICD_BASE			(0x0b000000)
+#define GICC_BASE			(0x0b002000)
+
+/* Clocks: (from CLK_CTL_BASE)  */
+#define GPLL0_STATUS			(0x21000)
+#define APCS_GPLL_ENA_VOTE		(0x45000)
+#define APCS_CLOCK_BRANCH_ENA_VOTE	(0x45004)
+
+/* BLSP1 AHB clock (root clock for BLSP) */
+#define BLSP1_AHB_CBCR			0x1008
+
+/* Uart clock control registers */
+#define BLSP1_UART2_BCR			(0x3028)
+#define BLSP1_UART2_APPS_CBCR		(0x302C)
+#define BLSP1_UART2_APPS_CMD_RCGR	(0x3034)
+#define BLSP1_UART2_APPS_CFG_RCGR	(0x3038)
+#define BLSP1_UART2_APPS_M		(0x303C)
+#define BLSP1_UART2_APPS_N		(0x3040)
+#define BLSP1_UART2_APPS_D		(0x3044)
+
+/* SD controller clock control registers */
+#define SDCC_BCR(n)			(((n) * 0x1000) + 0x41000)
+#define SDCC_CMD_RCGR(n)		(((n) * 0x1000) + 0x41004)
+#define SDCC_CFG_RCGR(n)		(((n) * 0x1000) + 0x41008)
+#define SDCC_M(n)			(((n) * 0x1000) + 0x4100C)
+#define SDCC_N(n)			(((n) * 0x1000) + 0x41010)
+#define SDCC_D(n)			(((n) * 0x1000) + 0x41014)
+#define SDCC_APPS_CBCR(n)		(((n) * 0x1000) + 0x41018)
+#define SDCC_AHB_CBCR(n)		(((n) * 0x1000) + 0x4101C)
+
+#endif
diff --git a/arch/arm/mach-snapdragon/pinctrl-qcs404.c b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
new file mode 100644
index 00000000000..889ead0f572
--- /dev/null
+++ b/arch/arm/mach-snapdragon/pinctrl-qcs404.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 pinctrl
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include "pinctrl-snapdragon.h"
+#include <common.h>
+
+#define MAX_PIN_NAME_LEN 32
+static char pin_name[MAX_PIN_NAME_LEN] __section(".data");
+static const char * const msm_pinctrl_pins[] = {
+	"SDC1_RCLK",
+	"SDC1_CLK",
+	"SDC1_CMD",
+	"SDC1_DATA",
+	"SDC2_CLK",
+	"SDC2_CMD",
+	"SDC2_DATA",
+};
+
+static const struct pinctrl_function msm_pinctrl_functions[] = {
+	{"blsp_uart2", 1},
+};
+
+static const char *qcs404_get_function_name(struct udevice *dev,
+					    unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].name;
+}
+
+static const char *qcs404_get_pin_name(struct udevice *dev,
+				       unsigned int selector)
+{
+	if (selector < 120) {
+		snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
+		return pin_name;
+	} else {
+		return msm_pinctrl_pins[selector - 120];
+	}
+}
+
+static unsigned int qcs404_get_function_mux(unsigned int selector)
+{
+	return msm_pinctrl_functions[selector].val;
+}
+
+struct msm_pinctrl_data qcs404_data = {
+	.pin_count = 126,
+	.functions_count = ARRAY_SIZE(msm_pinctrl_functions),
+	.get_function_name = qcs404_get_function_name,
+	.get_function_mux = qcs404_get_function_mux,
+	.get_pin_name = qcs404_get_pin_name,
+};
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
index d1c560dd401..c2148a5d0a0 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.c
@@ -119,6 +119,7 @@ static const struct udevice_id msm_pinctrl_ids[] = {
 #ifdef CONFIG_SDM845
 	{ .compatible = "qcom,tlmm-sdm845", .data = (ulong)&sdm845_data },
 #endif
+	{ .compatible = "qcom,tlmm-qcs404", .data = (ulong)&qcs404_data },
 	{ }
 };
 
diff --git a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
index ea524312a04..178ee01a41f 100644
--- a/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
+++ b/arch/arm/mach-snapdragon/pinctrl-snapdragon.h
@@ -28,5 +28,6 @@ struct pinctrl_function {
 extern struct msm_pinctrl_data apq8016_data;
 extern struct msm_pinctrl_data apq8096_data;
 extern struct msm_pinctrl_data sdm845_data;
+extern struct msm_pinctrl_data qcs404_data;
 
 #endif
diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c
new file mode 100644
index 00000000000..b7409031a03
--- /dev/null
+++ b/arch/arm/mach-snapdragon/sysmap-qcs404.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Qualcomm QCS404 memory map
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <asm/armv8/mmu.h>
+
+static struct mm_region qcs404_mem_map[] = {
+	{
+		.virt = 0x0UL, /* Peripheral block */
+		.phys = 0x0UL, /* Peripheral block */
+		.size = 0x8000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		.virt = 0x80000000UL, /* DDR */
+		.phys = 0x80000000UL, /* DDR */
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_INNER_SHARE
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = qcs404_mem_map;
diff --git a/board/qualcomm/dragonboard845c/Kconfig b/board/qualcomm/dragonboard845c/Kconfig
new file mode 100644
index 00000000000..52fdff288d5
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/Kconfig
@@ -0,0 +1,12 @@
+if TARGET_DRAGONBOARD845C
+
+config SYS_BOARD
+	default "dragonboard845c"
+
+config SYS_CONFIG_NAME
+	default "dragonboard845c"
+
+config SYS_VENDOR
+	default "qualcomm"
+
+endif
diff --git a/board/qualcomm/dragonboard845c/MAINTAINERS b/board/qualcomm/dragonboard845c/MAINTAINERS
new file mode 100644
index 00000000000..e555953df69
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/MAINTAINERS
@@ -0,0 +1,6 @@
+Qualcomm Robotics RB3 Development Platform (dragonboard845c)
+M:	Sumit Garg <sumit.garg@linaro.org>
+S:	Maintained
+F:	board/qualcomm/dragonboard845c/
+F:	include/configs/dragonboard845c.h
+F:	configs/dragonboard845c_defconfig
diff --git a/board/qualcomm/dragonboard845c/Makefile b/board/qualcomm/dragonboard845c/Makefile
new file mode 100644
index 00000000000..0abefdaf365
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/Makefile
@@ -0,0 +1,9 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+#
+# This empty file prevents make error.
+# Board logic defined in board/qualcomm/common/sdm845.c, no custom logic for dragonboard845c so far.
+#
+
+obj-y += dragonboard845c.o
diff --git a/board/qualcomm/dragonboard845c/db845c.its b/board/qualcomm/dragonboard845c/db845c.its
new file mode 100644
index 00000000000..a2621340d13
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/db845c.its
@@ -0,0 +1,63 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Various kernels, ramdisks and FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel-1 {
+			description = "5.15.0-qcomlt-arm64";
+			data = /incbin/("./db845c_imgs/Image.gz--5.15-r0-dragonboard-845c-20211218193034-511.bin");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <0x80000000>;
+			entry = <0x80000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		ramdisk-1 {
+			description = "initramfs-test-full-image-dragonboard-845c";
+			data = /incbin/("./db845c_imgs/initramfs-test-full-image-dragonboard-845c-20211218193034-511.rootfs.cpio.gz");
+			type = "ramdisk";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <00000000>;
+			entry = <00000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-1 {
+			description = "sdm845-db845c-fdt";
+			data = /incbin/("./db845c_imgs/sdm845-db845c--5.15-r0-dragonboard-845c-20211218193034.dtb");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			description = "db845c kernel-5.15.0 configuration";
+			kernel = "kernel-1";
+			ramdisk = "ramdisk-1";
+			fdt = "fdt-1";
+		};
+	};
+};
diff --git a/board/qualcomm/dragonboard845c/dragonboard845c.c b/board/qualcomm/dragonboard845c/dragonboard845c.c
new file mode 100644
index 00000000000..c7685de306c
--- /dev/null
+++ b/board/qualcomm/dragonboard845c/dragonboard845c.c
@@ -0,0 +1,9 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * This empty file prevents make linking error.
+ * No custom logic for dragonboard845c so far.
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+void noop(void) {}
diff --git a/board/qualcomm/qcs404-evb/Kconfig b/board/qualcomm/qcs404-evb/Kconfig
new file mode 100644
index 00000000000..32657c7d5e3
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/Kconfig
@@ -0,0 +1,15 @@
+if TARGET_QCS404EVB
+
+config SYS_BOARD
+	default "qcs404-evb"
+
+config SYS_VENDOR
+	default "qualcomm"
+
+config SYS_SOC
+	default "qcs404"
+
+config SYS_CONFIG_NAME
+	default "qcs404-evb"
+
+endif
diff --git a/board/qualcomm/qcs404-evb/MAINTAINERS b/board/qualcomm/qcs404-evb/MAINTAINERS
new file mode 100644
index 00000000000..0a2e194ff60
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/MAINTAINERS
@@ -0,0 +1,6 @@
+Qualcomm Technologies, Inc. QCS404 evaluation board
+M:	Sumit Garg <sumit.garg@linaro.org>
+S:	Maintained
+F:	board/qualcomm/qcs404-evb/
+F:	include/configs/qcs404-evb.h
+F:	configs/qcs404evb_defconfig
diff --git a/board/qualcomm/qcs404-evb/Makefile b/board/qualcomm/qcs404-evb/Makefile
new file mode 100644
index 00000000000..4665827e085
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+#
+
+obj-y += qcs404-evb.o
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c
new file mode 100644
index 00000000000..f1e6e7f7eb5
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/qcs404-evb.c
@@ -0,0 +1,33 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Board init file for QCS404-EVB
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <dm.h>
+#include <env.h>
+#include <init.h>
+#include <asm/cache.h>
+#include <asm/global_data.h>
+#include <fdt_support.h>
+#include <asm/arch/dram.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+int dram_init(void)
+{
+	return fdtdec_setup_mem_size_base();
+}
+
+int board_init(void)
+{
+	return 0;
+}
+
+void reset_cpu(void)
+{
+	psci_system_reset();
+}
diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.its b/board/qualcomm/qcs404-evb/qcs404-evb.its
new file mode 100644
index 00000000000..c9822827c99
--- /dev/null
+++ b/board/qualcomm/qcs404-evb/qcs404-evb.its
@@ -0,0 +1,64 @@
+/*
+ * U-Boot uImage source file with multiple kernels, ramdisks and FDT blobs
+ */
+
+/dts-v1/;
+
+/ {
+	description = "Various kernels, ramdisks and FDT blobs";
+	#address-cells = <1>;
+
+	images {
+		kernel-1 {
+			description = "5.18.0-rc1";
+			data = /incbin/("./qcs404_imgs/Image.gz");
+			type = "kernel";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <0x80000000>;
+			entry = <0x80000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		ramdisk-1 {
+			description = "Initial ramdisk";
+			data = /incbin/("./qcs404_imgs/initramfs-tiny-image-qemuarm64-20220618074058-1169.rootfs.cpio.gz");
+			type = "ramdisk";
+			arch = "arm64";
+			os = "linux";
+			compression = "gzip";
+			load = <00000000>;
+			entry = <00000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+		fdt-1 {
+			description = "qcs404-evb-fdt";
+			data = /incbin/("./qcs404_imgs/qcs404-evb-4000.dtb");
+			type = "flat_dt";
+			arch = "arm64";
+			compression = "none";
+			load = <0x83000000>;
+			hash-1 {
+				algo = "sha1";
+			};
+		};
+
+	};
+
+	configurations {
+		default = "config-1";
+
+		config-1 {
+			description = "qcs404-evb kernel-5.18.0-rc1 configuration";
+			kernel = "kernel-1";
+			ramdisk = "ramdisk-1";
+			fdt = "fdt-1";
+		};
+	};
+};
diff --git a/board/siemens/iot2050/Kconfig b/board/siemens/iot2050/Kconfig
index 8f634c172c1..063142a43bf 100644
--- a/board/siemens/iot2050/Kconfig
+++ b/board/siemens/iot2050/Kconfig
@@ -9,7 +9,7 @@
 config TARGET_IOT2050_A53
 	bool "IOT2050 running on A53"
 	select ARM64
-	select SOC_K3_AM6
+	select SOC_K3_AM654
 	select BOARD_LATE_INIT
 	select SYS_DISABLE_DCACHE_OPS
 	select BINMAN
diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c
index 2cb5b1cb3fc..b97fedddd5e 100644
--- a/board/ti/am335x/board.c
+++ b/board/ti/am335x/board.c
@@ -966,10 +966,20 @@ int board_fit_config_name_match(const char *name)
 		return 0;
 	else if (board_is_icev2() && !strcmp(name, "am335x-icev2"))
 		return 0;
-	else if (board_is_bben() && !strcmp(name, "am335x-sancloud-bbe"))
-		return 0;
-	else
-		return -1;
+	else if (board_is_bben()) {
+		char subtype_id = board_ti_get_config()[1];
+
+		if (subtype_id == 'L') {
+			if (!strcmp(name, "am335x-sancloud-bbe-lite"))
+				return 0;
+		} else if (subtype_id == 'I') {
+			if (!strcmp(name, "am335x-sancloud-bbe-extended-wifi"))
+				return 0;
+		} else if (!strcmp(name, "am335x-sancloud-bbe")) {
+			return 0;
+		}
+	}
+	return -1;
 }
 #endif
 
diff --git a/board/ti/am335x/mux.c b/board/ti/am335x/mux.c
index fed737fa099..7d31adec142 100644
--- a/board/ti/am335x/mux.c
+++ b/board/ti/am335x/mux.c
@@ -401,8 +401,13 @@ void enable_board_pin_mux(void)
 		configure_module_pin_mux(mmc0_pin_mux_sk_evm);
 	} else if (board_is_bone_lt()) {
 		if (board_is_bben()) {
+			char subtype_id = board_ti_get_config()[1];
+
 			/* SanCloud Beaglebone LT Enhanced pinmux */
 			configure_module_pin_mux(rgmii1_pin_mux);
+
+			if (subtype_id == 'L')
+				configure_module_pin_mux(spi0_pin_mux);
 		} else {
 			/* Beaglebone LT pinmux */
 			configure_module_pin_mux(mii1_pin_mux);
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 16a7476d9c4..4765b13ba0c 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -10,7 +10,7 @@ choice
 config TARGET_AM654_A53_EVM
 	bool "TI K3 based AM654 EVM running on A53"
 	select ARM64
-	select SOC_K3_AM6
+	select SOC_K3_AM654
 	select SYS_DISABLE_DCACHE_OPS
 	select BOARD_LATE_INIT
 	imply TI_I2C_BOARD_DETECT
@@ -19,7 +19,7 @@ config TARGET_AM654_R5_EVM
 	bool "TI K3 based AM654 EVM running on R5"
 	select CPU_V7R
 	select SYS_THUMB_BUILD
-	select SOC_K3_AM6
+	select SOC_K3_AM654
 	select K3_LOAD_SYSFW
 	select K3_AM654_DDRSS
 	imply SYS_K3_SPL_ATF
diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c
index 7182a8cad1a..8a0a506a3e3 100644
--- a/board/ti/am65x/evm.c
+++ b/board/ti/am65x/evm.c
@@ -115,16 +115,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
 		return ret;
 	}
 
-#if defined(CONFIG_TI_SECURE_DEVICE)
-	/* Make Crypto HW reserved for secure world use */
-	ret = fdt_disable_node(blob, "/bus@100000/crypto@4e00000");
-	if (ret < 0)
-		ret = fdt_disable_node(blob,
-				       "/interconnect@100000/crypto@4E00000");
-	if (ret)
-		printf("%s: disabling SA2UL failed %d\n", __func__, ret);
-#endif
-
 	return 0;
 }
 #endif
diff --git a/cmd/ti/ddr3.c b/cmd/ti/ddr3.c
index be937a7531d..aaaedfe9735 100644
--- a/cmd/ti/ddr3.c
+++ b/cmd/ti/ddr3.c
@@ -286,7 +286,7 @@ static int do_ddr_test(struct cmd_tbl *cmdtp,
 
 	if ((argc == 4) && (strncmp(argv[1], "ecc_err", 8) == 0)) {
 		if (!is_ecc_enabled()) {
-			puts("ECC not enabled. Please Enable ECC any try again\n");
+			puts("ECC not enabled. Please Enable ECC and try again\n");
 			return CMD_RET_FAILURE;
 		}
 
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index b8c21f557f0..2352fc9d6d2 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -256,7 +256,9 @@ config SPL_LDSCRIPT
 
 config SPL_TEXT_BASE
 	hex "SPL Text Base"
-	default ISW_ENTRY_ADDR if AM43XX || AM33XX || OMAP54XX || ARCH_KEYSTONE
+	default 0x402F4000 if AM43XX
+	default 0x402F0400 if AM33XX
+	default 0x40301350 if OMAP54XX
 	default 0x10060 if MACH_SUN50I || MACH_SUN50I_H5 || MACH_SUN9I
 	default 0x20060 if SUN50I_GEN_H6
 	default 0x00060 if ARCH_SUNXI
diff --git a/configs/am335x_evm_defconfig b/configs/am335x_evm_defconfig
index b5801094e8c..b500ed0fdd8 100644
--- a/configs/am335x_evm_defconfig
+++ b/configs/am335x_evm_defconfig
@@ -55,7 +55,7 @@ CONFIG_MTDIDS_DEFAULT="nand0=nand.0"
 CONFIG_MTDPARTS_DEFAULT="mtdparts=nand.0:128k(NAND.SPL),128k(NAND.SPL.backup1),128k(NAND.SPL.backup2),128k(NAND.SPL.backup3),256k(NAND.u-boot-spl-os),1m(NAND.u-boot),128k(NAND.u-boot-env),128k(NAND.u-boot-env.backup1),8m(NAND.kernel),-(NAND.file-system)"
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
+CONFIG_OF_LIST="am335x-evm am335x-bone am335x-sancloud-bbe am335x-sancloud-bbe-lite am335x-sancloud-bbe-extended-wifi am335x-boneblack am335x-evmsk am335x-bonegreen am335x-icev2 am335x-pocketbeagle"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
 CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
diff --git a/configs/am335x_hs_evm_defconfig b/configs/am335x_hs_evm_defconfig
index bb03e487f87..e10f0fdf39a 100644
--- a/configs/am335x_hs_evm_defconfig
+++ b/configs/am335x_hs_evm_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_AM33XX=y
diff --git a/configs/am335x_hs_evm_uart_defconfig b/configs/am335x_hs_evm_uart_defconfig
index ac451026b09..7da2defb09e 100644
--- a/configs/am335x_hs_evm_uart_defconfig
+++ b/configs/am335x_hs_evm_uart_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0x40301950
+CONFIG_SPL_TEXT_BASE=0x40301950
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_DEFAULT_DEVICE_TREE="am335x-evm"
 CONFIG_AM33XX=y
diff --git a/configs/am43xx_evm_usbhost_boot_defconfig b/configs/am43xx_evm_usbhost_boot_defconfig
index 8acf06d8ad8..2cdc208676a 100644
--- a/configs/am43xx_evm_usbhost_boot_defconfig
+++ b/configs/am43xx_evm_usbhost_boot_defconfig
@@ -2,7 +2,7 @@ CONFIG_ARM=y
 CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_OMAP2PLUS=y
-CONFIG_ISW_ENTRY_ADDR=0x40300350
+CONFIG_SPL_TEXT_BASE=0x40300350
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
diff --git a/configs/am43xx_hs_evm_defconfig b/configs/am43xx_hs_evm_defconfig
index 6613177e0f4..516686b7c8d 100644
--- a/configs/am43xx_hs_evm_defconfig
+++ b/configs/am43xx_hs_evm_defconfig
@@ -3,12 +3,11 @@ CONFIG_SKIP_LOWLEVEL_INIT=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0x403018e0
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_ENV_SIZE=0x10000
 CONFIG_DM_GPIO=y
 CONFIG_DEFAULT_DEVICE_TREE="am437x-gp-evm"
-CONFIG_SPL_TEXT_BASE=0x403018E0
+CONFIG_SPL_TEXT_BASE=0x403018e0
 CONFIG_AM43XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
diff --git a/configs/am43xx_hs_evm_qspi_defconfig b/configs/am43xx_hs_evm_qspi_defconfig
new file mode 100644
index 00000000000..5cf447704da
--- /dev/null
+++ b/configs/am43xx_hs_evm_qspi_defconfig
@@ -0,0 +1,74 @@
+CONFIG_ARM=y
+CONFIG_ARCH_CPU_INIT=y
+# CONFIG_SYS_THUMB_BUILD is not set
+CONFIG_ARCH_OMAP2PLUS=y
+CONFIG_TI_SECURE_DEVICE=y
+CONFIG_ISW_ENTRY_ADDR=0x300018e0
+CONFIG_ENV_SIZE=0x10000
+CONFIG_ENV_OFFSET=0x110000
+CONFIG_ENV_SECT_SIZE=0x10000
+CONFIG_DM_GPIO=y
+CONFIG_DEFAULT_DEVICE_TREE="am43x-epos-evm"
+CONFIG_AM43XX=y
+CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
+CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
+CONFIG_TI_SECURE_EMIF_PROTECTED_REGION_SIZE=0x01c00000
+CONFIG_ENV_OFFSET_REDUND=0x120000
+CONFIG_DISTRO_DEFAULTS=y
+CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y
+CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00
+CONFIG_QSPI_BOOT=y
+CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd"
+CONFIG_SYS_CONSOLE_INFO_QUIET=y
+CONFIG_BOARD_EARLY_INIT_F=y
+# CONFIG_MISC_INIT_R is not set
+CONFIG_SYS_MAXARGS=64
+CONFIG_CMD_ASKENV=y
+CONFIG_CMD_DFU=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_BOOTP_DNS2=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_LIST="am4372-generic am437x-sk-evm am437x-idk-evm"
+CONFIG_DTB_RESELECT=y
+CONFIG_MULTI_DTB_FIT=y
+CONFIG_ENV_OVERWRITE=y
+CONFIG_ENV_IS_IN_SPI_FLASH=y
+CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_SYS_RELOC_GD_ENV_ADDR=y
+CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y
+CONFIG_VERSION_VARIABLE=y
+CONFIG_NET_RETRY_COUNT=10
+CONFIG_BOOTP_SEND_HOSTNAME=y
+CONFIG_SYS_RX_ETH_BUFFER=64
+CONFIG_DM=y
+CONFIG_DFU_MMC=y
+CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
+CONFIG_SPL_SYS_I2C_LEGACY=y
+CONFIG_MMC_OMAP_HS=y
+CONFIG_SF_DEFAULT_SPEED=48000000
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_MII=y
+CONFIG_DRIVER_TI_CPSW=y
+CONFIG_SYS_NS16550=y
+CONFIG_SPI=y
+CONFIG_TI_QSPI=y
+CONFIG_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_XHCI_OMAP=y
+CONFIG_USB_DWC3=y
+CONFIG_USB_DWC3_OMAP=y
+CONFIG_USB_DWC3_PHY_OMAP=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0403
+CONFIG_USB_GADGET_PRODUCT_NUM=0xbd00
+CONFIG_USB_GADGET_DOWNLOAD=y
diff --git a/configs/am57xx_hs_evm_defconfig b/configs/am57xx_hs_evm_defconfig
index aa0b466d954..4b01b605138 100644
--- a/configs/am57xx_hs_evm_defconfig
+++ b/configs/am57xx_hs_evm_defconfig
@@ -5,7 +5,7 @@ CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
-CONFIG_DEFAULT_DEVICE_TREE="am57xx-beagle-x15"
+CONFIG_DEFAULT_DEVICE_TREE="am572x-idk"
 CONFIG_OMAP54XX=y
 CONFIG_TI_SECURE_EMIF_REGION_START=0xbdb00000
 CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE=0x02000000
@@ -41,6 +41,7 @@ CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x40000
+CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_BOOTM_LEN=0x4000000
 CONFIG_CMD_ADTIMG=y
@@ -55,7 +56,7 @@ CONFIG_BOOTP_DNS2=y
 CONFIG_CMD_AVB=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
-CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am572x-idk am571x-idk am574x-idk"
+CONFIG_OF_LIST="am57xx-beagle-x15 am57xx-beagle-x15-revb1 am57xx-beagle-x15-revc am5729-beagleboneai am572x-idk am571x-idk am574x-idk"
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
@@ -68,9 +69,15 @@ CONFIG_BOOTP_SEND_HOSTNAME=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
+CONFIG_SPL_REGMAP=y
+CONFIG_SPL_SYSCON=y
+CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_DWC_AHCI=y
+CONFIG_CLK=y
+CONFIG_CLK_CDCE9XX=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
+CONFIG_DFU_SF=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
 CONFIG_FASTBOOT_BUF_ADDR=0x82000000
 CONFIG_FASTBOOT_BUF_SIZE=0x2F000000
diff --git a/configs/am57xx_hs_evm_usb_defconfig b/configs/am57xx_hs_evm_usb_defconfig
index 2ac7028ab09..ec5434219d8 100644
--- a/configs/am57xx_hs_evm_usb_defconfig
+++ b/configs/am57xx_hs_evm_usb_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0x40306d50
+CONFIG_SPL_TEXT_BASE=0x40306d50
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_NR_DRAM_BANKS=2
 CONFIG_DM_GPIO=y
diff --git a/configs/am62x_evm_r5_defconfig b/configs/am62x_evm_r5_defconfig
index deafb92fc14..e26e9dc800f 100644
--- a/configs/am62x_evm_r5_defconfig
+++ b/configs/am62x_evm_r5_defconfig
@@ -97,3 +97,6 @@ CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
 CONFIG_LIB_RATIONAL=y
 CONFIG_SPL_LIB_RATIONAL=y
+CONFIG_ESM_K3=y
+CONFIG_SPL_MISC=y
+CONFIG_SPL_DRIVERS_MISC=y
diff --git a/configs/am65x_evm_a53_defconfig b/configs/am65x_evm_a53_defconfig
index fabb116ba44..0ca0ebc8c07 100644
--- a/configs/am65x_evm_a53_defconfig
+++ b/configs/am65x_evm_a53_defconfig
@@ -6,7 +6,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_TARGET_AM654_A53_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
diff --git a/configs/am65x_evm_r5_defconfig b/configs/am65x_evm_r5_defconfig
index 5232b979709..7622495b5f6 100644
--- a/configs/am65x_evm_r5_defconfig
+++ b/configs/am65x_evm_r5_defconfig
@@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_AM654_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
diff --git a/configs/am65x_evm_r5_usbdfu_defconfig b/configs/am65x_evm_r5_usbdfu_defconfig
index edfd9a74627..b096388103e 100644
--- a/configs/am65x_evm_r5_usbdfu_defconfig
+++ b/configs/am65x_evm_r5_usbdfu_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_MISC=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_AM654_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
diff --git a/configs/am65x_evm_r5_usbmsc_defconfig b/configs/am65x_evm_r5_usbmsc_defconfig
index e7e22264732..641daa63537 100644
--- a/configs/am65x_evm_r5_usbmsc_defconfig
+++ b/configs/am65x_evm_r5_usbmsc_defconfig
@@ -6,7 +6,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_AM654_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
diff --git a/configs/am65x_hs_evm_a53_defconfig b/configs/am65x_hs_evm_a53_defconfig
index 3ce290467ab..1b3b25b2cb3 100644
--- a/configs/am65x_hs_evm_a53_defconfig
+++ b/configs/am65x_hs_evm_a53_defconfig
@@ -7,7 +7,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x8000
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_TARGET_AM654_A53_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
diff --git a/configs/am65x_hs_evm_r5_defconfig b/configs/am65x_hs_evm_r5_defconfig
index 6e63f0e8807..d3a0420b1c2 100644
--- a/configs/am65x_hs_evm_r5_defconfig
+++ b/configs/am65x_hs_evm_r5_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_AM654_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
diff --git a/configs/dra7xx_hs_evm_usb_defconfig b/configs/dra7xx_hs_evm_usb_defconfig
index 14d2adfa058..18535429c13 100644
--- a/configs/dra7xx_hs_evm_usb_defconfig
+++ b/configs/dra7xx_hs_evm_usb_defconfig
@@ -1,7 +1,7 @@
 CONFIG_ARM=y
 CONFIG_ARCH_OMAP2PLUS=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0x40306d50
+CONFIG_SPL_TEXT_BASE=0x40306d50
 CONFIG_SYS_MALLOC_F_LEN=0x18000
 CONFIG_TI_COMMON_CMD_OPTIONS=y
 CONFIG_NR_DRAM_BANKS=2
diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig
new file mode 100644
index 00000000000..cf1a1d25cff
--- /dev/null
+++ b/configs/dragonboard845c_defconfig
@@ -0,0 +1,29 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c"
+CONFIG_TARGET_DRAGONBOARD845C=y
+CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C"
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=5
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_CMD_GPIO=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_MSM_GPIO=y
+CONFIG_PM8916_GPIO=y
+CONFIG_PINCTRL=y
+CONFIG_DM_PMIC=y
+CONFIG_PMIC_PM8916=y
+CONFIG_MSM_GENI_SERIAL=y
+CONFIG_SPMI_MSM=y
+CONFIG_LMB_MAX_REGIONS=64
diff --git a/configs/iot2050_defconfig b/configs/iot2050_defconfig
index b50b5d09382..203748100a1 100644
--- a/configs/iot2050_defconfig
+++ b/configs/iot2050_defconfig
@@ -7,7 +7,7 @@ CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_NR_DRAM_BANKS=2
-CONFIG_SOC_K3_AM6=y
+CONFIG_SOC_K3_AM654=y
 CONFIG_TARGET_IOT2050_A53=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
diff --git a/configs/j721e_hs_evm_a72_defconfig b/configs/j721e_hs_evm_a72_defconfig
index a1c8a374aea..034a71189f8 100644
--- a/configs/j721e_hs_evm_a72_defconfig
+++ b/configs/j721e_hs_evm_a72_defconfig
@@ -10,7 +10,6 @@ CONFIG_NR_DRAM_BANKS=2
 CONFIG_SOC_K3_J721E=y
 CONFIG_TARGET_J721E_A72_EVM=y
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-common-proc-board"
@@ -19,7 +18,6 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x700000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -33,7 +31,7 @@ CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x81000000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
 CONFIG_OF_BOARD_SETUP=y
-CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlaystring; run run_fit"
+CONFIG_BOOTCOMMAND="run findfdt; run envboot; run init_${boot}; run main_cpsw0_qsgmii_phyinit; run boot_rprocs; run get_fit_${boot}; run get_overlay_${boot}; run run_fit"
 CONFIG_LOGLEVEL=7
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
@@ -44,6 +42,9 @@ CONFIG_SPL_SYS_MALLOC_SIMPLE=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SYS_SPL_MALLOC=y
 CONFIG_SYS_SPL_MALLOC_SIZE=0x800000
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400
+CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
 CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img"
 CONFIG_SPL_I2C=y
@@ -53,15 +54,20 @@ CONFIG_SPL_DM_SPI_FLASH=y
 CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
+CONFIG_SPL_RAM_SUPPORT=y
+CONFIG_SPL_RAM_DEVICE=y
 # CONFIG_SPL_SPI_FLASH_TINY is not set
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x280000
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_CMD_ASKENV=y
 CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
 CONFIG_CMD_GPT=y
 CONFIG_CMD_I2C=y
 CONFIG_CMD_MMC=y
@@ -74,20 +80,23 @@ CONFIG_CMD_USB_MASS_STORAGE=y
 CONFIG_CMD_TIME=y
 CONFIG_CMD_EXT4_WRITE=y
 CONFIG_MTDIDS_DEFAULT="nor0=47040000.spi.0,nor0=47034000.hyperbus"
-CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),128k(ospi.env),128k(ospi.env.backup),1m(ospi.sysfw),-@8m(ospi.rootfs);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
+CONFIG_MTDPARTS_DEFAULT="mtdparts=47040000.spi.0:512k(ospi.tiboot3),2m(ospi.tispl),4m(ospi.u-boot),256k(ospi.env),1m(ospi.sysfw),256k(ospi.env.backup),57344k@8m(ospi.rootfs),256k(ospi.phypattern);47034000.hyperbus:512k(hbmc.tiboot3),2m(hbmc.tispl),4m(hbmc.u-boot),256k(hbmc.env),1m(hbmc.sysfw),-@8m(hbmc.rootfs)"
 CONFIG_CMD_UBI=y
 CONFIG_MMC_SPEED_MODE_SET=y
 # CONFIG_ISO_PARTITION is not set
 # CONFIG_SPL_EFI_PARTITION is not set
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_OF_LIST="k3-j721e-common-proc-board k3-j721e-sk"
+CONFIG_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT=y
 CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
+CONFIG_ENV_IS_NOWHERE=y
+CONFIG_ENV_IS_IN_FAT=y
 CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
+CONFIG_ENV_FAT_DEVICE_AND_PART="1:1"
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_NET_RANDOM_ETHADDR=y
 CONFIG_DM=y
 CONFIG_SPL_DM=y
@@ -103,6 +112,8 @@ CONFIG_CLK_TI_SCI=y
 CONFIG_DFU_MMC=y
 CONFIG_DFU_RAM=y
 CONFIG_DFU_SF=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x20000
+CONFIG_SYS_DFU_MAX_FILE_SIZE=0x800000
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_USB_FUNCTION_FASTBOOT=y
@@ -112,10 +123,18 @@ CONFIG_FASTBOOT_FLASH=y
 CONFIG_FASTBOOT_FLASH_MMC_DEV=0
 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y
 CONFIG_TI_SCI_PROTOCOL=y
+CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
 CONFIG_SYS_I2C_OMAP24XX=y
 CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_MMC_IO_VOLTAGE=y
+CONFIG_MMC_UHS_SUPPORT=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_MMC_SDHCI_ADMA=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
@@ -133,10 +152,16 @@ CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_STMICRO=y
 # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set
 CONFIG_SPI_FLASH_MTD=y
+CONFIG_MULTIPLEXER=y
+CONFIG_MUX_MMIO=y
 CONFIG_PHY_TI_DP83867=y
 CONFIG_PHY_FIXED=y
 CONFIG_DM_ETH=y
 CONFIG_TI_AM65_CPSW_NUSS=y
+CONFIG_PHY=y
+CONFIG_SPL_PHY=y
+CONFIG_PHY_CADENCE_SIERRA=y
+CONFIG_PHY_J721E_WIZ=y
 CONFIG_PINCTRL=y
 # CONFIG_PINCTRL_GENERIC is not set
 CONFIG_SPL_PINCTRL=y
@@ -144,7 +169,11 @@ CONFIG_SPL_PINCTRL=y
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
 CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_REGULATOR_FIXED=y
+CONFIG_DM_REGULATOR_GPIO=y
 CONFIG_RAM=y
+CONFIG_SPL_RAM=y
 CONFIG_REMOTEPROC_TI_K3_DSP=y
 CONFIG_REMOTEPROC_TI_K3_R5F=y
 CONFIG_DM_RESET=y
@@ -170,6 +199,7 @@ CONFIG_USB_XHCI_HCD=y
 CONFIG_USB_CDNS3=y
 CONFIG_USB_CDNS3_GADGET=y
 CONFIG_USB_CDNS3_HOST=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
 CONFIG_USB_GADGET=y
 CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
 CONFIG_USB_GADGET_VENDOR_NUM=0x0451
diff --git a/configs/j721e_hs_evm_r5_defconfig b/configs/j721e_hs_evm_r5_defconfig
index add8da02056..9ae03ade0fd 100644
--- a/configs/j721e_hs_evm_r5_defconfig
+++ b/configs/j721e_hs_evm_r5_defconfig
@@ -2,14 +2,14 @@ CONFIG_ARM=y
 CONFIG_ARCH_K3=y
 CONFIG_TI_SECURE_DEVICE=y
 CONFIG_SYS_MALLOC_LEN=0x2000000
-CONFIG_SYS_MALLOC_F_LEN=0x55000
+CONFIG_SYS_MALLOC_F_LEN=0x70000
 CONFIG_SPL_GPIO=y
 CONFIG_SPL_LIBCOMMON_SUPPORT=y
 CONFIG_SPL_LIBGENERIC_SUPPORT=y
 CONFIG_SOC_K3_J721E=y
+CONFIG_K3_EARLY_CONS=y
 CONFIG_TARGET_J721E_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
-CONFIG_ENV_OFFSET=0x680000
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-j721e-r5-common-proc-board"
@@ -18,7 +18,6 @@ CONFIG_SPL_MMC=y
 CONFIG_SPL_SERIAL=y
 CONFIG_SPL_DRIVERS_MISC=y
 CONFIG_SPL_STACK_R_ADDR=0x82000000
-CONFIG_ENV_OFFSET_REDUND=0x700000
 CONFIG_SPL_FS_FAT=y
 CONFIG_SPL_LIBDISK_SUPPORT=y
 CONFIG_SPL_SPI_FLASH_SUPPORT=y
@@ -29,12 +28,14 @@ CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x41cf5bfc
 CONFIG_SPL_LOAD_FIT=y
 CONFIG_SPL_LOAD_FIT_ADDRESS=0x80080000
 # CONFIG_USE_SPL_FIT_GENERATOR is not set
+CONFIG_OF_BOARD_SETUP=y
 CONFIG_USE_BOOTCOMMAND=y
 # CONFIG_DISPLAY_CPUINFO is not set
 CONFIG_SPL_MAX_SIZE=0xc0000
 CONFIG_SPL_HAS_BSS_LINKER_SECTION=y
 CONFIG_SPL_BSS_START_ADDR=0x41cf5bfc
 CONFIG_SPL_BSS_MAX_SIZE=0xa000
+CONFIG_SPL_BOARD_INIT=y
 CONFIG_SPL_STACK_R=y
 CONFIG_SPL_SEPARATE_BSS=y
 CONFIG_SYS_SPL_MALLOC=y
@@ -42,11 +43,16 @@ CONFIG_HAS_CUSTOM_SPL_MALLOC_START=y
 CONFIG_CUSTOM_SYS_SPL_MALLOC_ADDR=0x84000000
 CONFIG_SYS_SPL_MALLOC_SIZE=0x1000000
 CONFIG_SPL_EARLY_BSS=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y
+CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400
 CONFIG_SPL_DMA=y
 CONFIG_SPL_ENV_SUPPORT=y
+CONFIG_SPL_FS_EXT4=y
 CONFIG_SPL_I2C=y
 CONFIG_SPL_DM_MAILBOX=y
+CONFIG_SPL_MTD_SUPPORT=y
 CONFIG_SPL_DM_SPI_FLASH=y
+CONFIG_SPL_NOR_SUPPORT=y
 CONFIG_SPL_DM_RESET=y
 CONFIG_SPL_POWER_DOMAIN=y
 CONFIG_SPL_RAM_SUPPORT=y
@@ -56,10 +62,13 @@ CONFIG_SPL_REMOTEPROC=y
 CONFIG_SPL_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPL_SPI_LOAD=y
 CONFIG_SYS_SPI_U_BOOT_OFFS=0x80000
+CONFIG_SPL_USB_GADGET=y
+CONFIG_SPL_DFU=y
 CONFIG_SPL_YMODEM_SUPPORT=y
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_MAXARGS=64
 CONFIG_SYS_BOOTM_LEN=0x4000000
+CONFIG_CMD_DFU=y
 # CONFIG_CMD_FLASH is not set
 CONFIG_CMD_GPT=y
 CONFIG_CMD_MMC=y
@@ -67,26 +76,33 @@ CONFIG_CMD_REMOTEPROC=y
 # CONFIG_CMD_SETEXPR is not set
 CONFIG_CMD_TIME=y
 CONFIG_CMD_FAT=y
+CONFIG_CMD_MTDPARTS=y
 CONFIG_OF_CONTROL=y
 CONFIG_SPL_OF_CONTROL=y
+CONFIG_SPL_MULTI_DTB_FIT=y
+CONFIG_SPL_OF_LIST="k3-j721e-r5-common-proc-board k3-j721e-r5-sk"
+CONFIG_SPL_MULTI_DTB_FIT_NO_COMPRESSION=y
 CONFIG_ENV_OVERWRITE=y
-CONFIG_ENV_IS_IN_MMC=y
-CONFIG_SYS_REDUNDAND_ENVIRONMENT=y
 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
-CONFIG_SYS_MMC_ENV_PART=1
 CONFIG_DM=y
 CONFIG_SPL_DM=y
 CONFIG_SPL_DM_SEQ_ALIAS=y
 CONFIG_REGMAP=y
 CONFIG_SPL_REGMAP=y
+CONFIG_SYSCON=y
+CONFIG_SPL_SYSCON=y
 CONFIG_SPL_OF_TRANSLATE=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
-CONFIG_CLK_TI_SCI=y
+CONFIG_SPL_CLK_CCF=y
+CONFIG_SPL_CLK_K3_PLL=y
+CONFIG_SPL_CLK_K3=y
+CONFIG_SYS_DFU_DATA_BUF_SIZE=0x5000
 CONFIG_DMA_CHANNELS=y
 CONFIG_TI_K3_NAVSS_UDMA=y
 CONFIG_TI_SCI_PROTOCOL=y
 CONFIG_DA8XX_GPIO=y
+CONFIG_DM_PCA953X=y
 CONFIG_DM_I2C=y
 CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
 CONFIG_SYS_I2C_OMAP24XX=y
@@ -94,11 +110,22 @@ CONFIG_DM_MAILBOX=y
 CONFIG_K3_SEC_PROXY=y
 CONFIG_FS_LOADER=y
 CONFIG_SPL_FS_LOADER=y
+CONFIG_ESM_K3=y
 CONFIG_K3_AVS0=y
+CONFIG_ESM_PMIC=y
+CONFIG_SUPPORT_EMMC_BOOT=y
+CONFIG_SPL_MMC_HS200_SUPPORT=y
 CONFIG_MMC_SDHCI=y
 CONFIG_SPL_MMC_SDHCI_ADMA=y
 CONFIG_MMC_SDHCI_AM654=y
 CONFIG_MTD=y
+CONFIG_DM_MTD=y
+CONFIG_MTD_NOR_FLASH=y
+CONFIG_CFI_FLASH=y
+CONFIG_SYS_FLASH_USE_BUFFER_WRITE=y
+CONFIG_FLASH_CFI_MTD=y
+CONFIG_SYS_FLASH_CFI=y
+CONFIG_HBMC_AM654=y
 CONFIG_DM_SPI_FLASH=y
 CONFIG_SPI_FLASH_SFDP_SUPPORT=y
 CONFIG_SPI_FLASH_STMICRO=y
@@ -108,7 +135,7 @@ CONFIG_SPL_PINCTRL=y
 # CONFIG_SPL_PINCTRL_GENERIC is not set
 CONFIG_PINCTRL_SINGLE=y
 CONFIG_POWER_DOMAIN=y
-CONFIG_TI_SCI_POWER_DOMAIN=y
+CONFIG_TI_POWER_DOMAIN=y
 CONFIG_DM_PMIC=y
 CONFIG_PMIC_TPS65941=y
 CONFIG_DM_REGULATOR=y
@@ -133,5 +160,18 @@ CONFIG_SYSRESET_TI_SCI=y
 CONFIG_TIMER=y
 CONFIG_SPL_TIMER=y
 CONFIG_OMAP_TIMER=y
+CONFIG_USB=y
+CONFIG_DM_USB_GADGET=y
+CONFIG_SPL_DM_USB_GADGET=y
+CONFIG_USB_CDNS3=y
+CONFIG_USB_CDNS3_GADGET=y
+CONFIG_SPL_USB_CDNS3_GADGET=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_MANUFACTURER="Texas Instruments"
+CONFIG_USB_GADGET_VENDOR_NUM=0x0451
+CONFIG_USB_GADGET_PRODUCT_NUM=0x6163
+CONFIG_USB_GADGET_DOWNLOAD=y
 CONFIG_FS_EXT4=y
 CONFIG_FS_FAT_MAX_CLUSTSIZE=16384
+CONFIG_LIB_RATIONAL=y
+CONFIG_SPL_LIB_RATIONAL=y
diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig
index 58c8c13b15a..ad6c8f8a34c 100644
--- a/configs/k2e_evm_defconfig
+++ b/configs/k2e_evm_defconfig
@@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
-CONFIG_ISW_ENTRY_ADDR=0xC100000
+CONFIG_SPL_TEXT_BASE=0xC100000
 CONFIG_SYS_TEXT_BASE=0xC000000
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig
index 1845bec5178..8f8d558075b 100644
--- a/configs/k2e_hs_evm_defconfig
+++ b/configs/k2e_hs_evm_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0xC100000
 CONFIG_SYS_TEXT_BASE=0xC000060
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2g_evm_defconfig b/configs/k2g_evm_defconfig
index b96d1fc7c1a..93c454b3441 100644
--- a/configs/k2g_evm_defconfig
+++ b/configs/k2g_evm_defconfig
@@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
-CONFIG_ISW_ENTRY_ADDR=0xC0A0000
+CONFIG_SPL_TEXT_BASE=0xC0A0000
 CONFIG_SYS_TEXT_BASE=0xC000000
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2g_hs_evm_defconfig b/configs/k2g_hs_evm_defconfig
index ef92bef10c7..33fd445420b 100644
--- a/configs/k2g_hs_evm_defconfig
+++ b/configs/k2g_hs_evm_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0xC0A0000
 CONFIG_SYS_TEXT_BASE=0xC000060
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig
index cfe5978e550..c9a53bb770d 100644
--- a/configs/k2hk_evm_defconfig
+++ b/configs/k2hk_evm_defconfig
@@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
-CONFIG_ISW_ENTRY_ADDR=0xC200000
+CONFIG_SPL_TEXT_BASE=0xC200000
 CONFIG_SYS_TEXT_BASE=0xC000000
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig
index 5caf3db2fe5..87addbd8ab1 100644
--- a/configs/k2hk_hs_evm_defconfig
+++ b/configs/k2hk_hs_evm_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0xC200000
 CONFIG_SYS_TEXT_BASE=0xC000060
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig
index 47d5bd14ac5..356b3b80458 100644
--- a/configs/k2l_evm_defconfig
+++ b/configs/k2l_evm_defconfig
@@ -4,7 +4,7 @@ CONFIG_SPL_SKIP_LOWLEVEL_INIT=y
 CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
-CONFIG_ISW_ENTRY_ADDR=0xC100000
+CONFIG_SPL_TEXT_BASE=0xC100000
 CONFIG_SYS_TEXT_BASE=0xC000000
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig
index 5c44ca922c4..9aa47f3b2a3 100644
--- a/configs/k2l_hs_evm_defconfig
+++ b/configs/k2l_hs_evm_defconfig
@@ -4,7 +4,6 @@ CONFIG_SYS_DCACHE_OFF=y
 CONFIG_ARCH_CPU_INIT=y
 CONFIG_ARCH_KEYSTONE=y
 CONFIG_TI_SECURE_DEVICE=y
-CONFIG_ISW_ENTRY_ADDR=0xC100000
 CONFIG_SYS_TEXT_BASE=0xC000060
 CONFIG_SYS_MALLOC_LEN=0x2000000
 CONFIG_SYS_MALLOC_F_LEN=0x400
diff --git a/configs/nokia_rx51_defconfig b/configs/nokia_rx51_defconfig
index 6c3a95cd069..3b559abf235 100644
--- a/configs/nokia_rx51_defconfig
+++ b/configs/nokia_rx51_defconfig
@@ -24,7 +24,6 @@ CONFIG_AUTOBOOT_MENU_SHOW=y
 CONFIG_USE_BOOTCOMMAND=y
 CONFIG_BOOTCOMMAND="run sdboot;run emmcboot;run attachboot;echo"
 CONFIG_USE_PREBOOT=y
-CONFIG_PREBOOT="run preboot"
 # CONFIG_SYS_DEVICE_NULLDEV is not set
 CONFIG_HUSH_PARSER=y
 CONFIG_SYS_PROMPT="Nokia RX-51 # "
diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig
new file mode 100644
index 00000000000..d45f6b2348b
--- /dev/null
+++ b/configs/qcs404evb_defconfig
@@ -0,0 +1,38 @@
+CONFIG_ARM=y
+CONFIG_SKIP_LOWLEVEL_INIT=y
+CONFIG_COUNTER_FREQUENCY=19000000
+CONFIG_POSITION_INDEPENDENT=y
+CONFIG_ARCH_SNAPDRAGON=y
+CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb"
+CONFIG_TARGET_QCS404EVB=y
+CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB"
+CONFIG_SYS_LOAD_ADDR=0x80000000
+CONFIG_FIT=y
+CONFIG_FIT_VERBOSE=y
+CONFIG_BOOTDELAY=5
+CONFIG_USE_BOOTARGS=y
+CONFIG_BOOTARGS="earlycon ignore_loglevel root= clk_ignore_unused"
+CONFIG_SAVE_PREV_BL_FDT_ADDR=y
+CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y
+# CONFIG_DISPLAY_CPUINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_MAXARGS=64
+CONFIG_SYS_CBSIZE=512
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_PART=y
+CONFIG_CMD_EXT2=y
+CONFIG_CMD_EXT4=y
+CONFIG_CMD_EXT4_WRITE=y
+CONFIG_CMD_FAT=y
+CONFIG_CMD_FS_GENERIC=y
+# CONFIG_NET is not set
+CONFIG_CLK=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_ADMA=y
+CONFIG_MMC_SDHCI_MSM=y
+CONFIG_PINCTRL=y
+CONFIG_MSM_SERIAL=y
+CONFIG_LMB_MAX_REGIONS=64
diff --git a/doc/board/qualcomm/index.rst b/doc/board/qualcomm/index.rst
index 10b98214e96..0f9c4299569 100644
--- a/doc/board/qualcomm/index.rst
+++ b/doc/board/qualcomm/index.rst
@@ -8,3 +8,4 @@ Qualcomm
 
    dragonboard410c
    sdm845
+   qcs404
diff --git a/doc/board/qualcomm/qcs404.rst b/doc/board/qualcomm/qcs404.rst
new file mode 100644
index 00000000000..bbb40b043b3
--- /dev/null
+++ b/doc/board/qualcomm/qcs404.rst
@@ -0,0 +1,79 @@
+.. SPDX-License-Identifier: GPL-2.0+
+.. sectionauthor:: Sumit Garg <sumit.garg@linaro.org>
+
+QCS404 EVB
+==========
+
+About this
+----------
+This document describes the information about Qualcomm QCS404 evaluation board
+and it's usage steps.
+
+U-Boot can be used as a replacement for Qualcomm's original ABL (UEFI) bootloader.
+It is loaded as an Android boot image through ABL
+
+Installation
+------------
+Build
+^^^^^
+Setup ``CROSS_COMPILE`` for aarch64 and build U-Boot for your board::
+
+	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
+	$ make qcs404evb_defconfig
+	$ make
+
+This will build ``u-boot.bin`` in the configured output directory.
+
+Generate FIT image
+^^^^^^^^^^^^^^^^^^
+A ``qcs404.its`` file can be found in ``board/qualcomm/qcs404-evb/`` directory.
+It expects a folder as ``qcs404_imgs/`` in the main directory containing
+pre-built kernel, dts and ramdisk images. See ``qcs404.its`` for full path to
+images.
+
+- Build FIT image::
+
+	mkimage -f qcs404-evb.its qcs404-evb.itb
+
+Pack android boot image
+^^^^^^^^^^^^^^^^^^^^^^^
+We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
+and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
+with appended dtb, so let's mimic linux to satisfy stock bootloader:
+
+- create dump dtb::
+
+	workdir=/tmp/prepare_payload
+	mkdir -p "$workdir"
+	cd "$workdir"
+	mock_dtb="$workdir"/payload_mock.dtb
+
+	dtc -I dts -O dtb -o "$mock_dtb" << EOF
+	/dts-v1/;
+	/ {
+		model = "Qualcomm Technologies, Inc. QCS404 EVB 4000";
+		compatible = "qcom,qcs404-evb-4000", "qcom,qcs404-evb", "qcom,qcs404";
+
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		memory@80000000 {
+			device_type = "memory";
+			/* We expect the bootloader to fill in the size */
+			reg = <0 0x80000000 0 0>;
+		};
+
+		chosen { };
+	};
+	EOF
+
+- gzip u-boot ``gzip u-boot.bin``
+- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
+
+Now we've got everything to build android boot image:::
+
+	mkbootimg --kernel u-boot.bin.gz-dtb \
+	--ramdisk qcs404-evb.itb --pagesize 4096 \
+	--base 0x80000000 --output boot.img
+
+Flash image on qcs404-evb using fastboot method.
diff --git a/doc/board/qualcomm/sdm845.rst b/doc/board/qualcomm/sdm845.rst
index b6642c95790..8ef47492877 100644
--- a/doc/board/qualcomm/sdm845.rst
+++ b/doc/board/qualcomm/sdm845.rst
@@ -35,9 +35,25 @@ Pack android boot image
 ^^^^^^^^^^^^^^^^^^^^^^^
 We'll assemble android boot image with ``u-boot.bin`` instead of linux kernel,
 and FIT image instead of ``initramfs``. Android bootloader expect gzipped kernel
-with appended dtb, so let's mimic linux to satisfy stock bootloader:
+with appended dtb, so let's mimic linux to satisfy stock bootloader.
 
-- create dump dtb::
+Boards
+------------
+starqlte
+^^^^^^^^^^^^
+
+The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
+based on the Qualcomm SDM845 SoC.
+
+Steps:
+
+- Build u-boot::
+
+	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
+	$ make starqltechn_defconfig
+	$ make
+
+- Create dump dtb::
 
 	workdir=/tmp/prepare_payload
 	mkdir -p "$workdir"
@@ -56,10 +72,15 @@ with appended dtb, so let's mimic linux to satisfy stock bootloader:
 	};
 	EOF
 
-- gzip u-boot ``gzip u-boot.bin``
-- append dtb to gzipped u-boot: ``cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb``
+- gzip u-boot::
+
+	gzip u-boot.bin
 
-Now we've got everything to build android boot image:::
+- Append dtb to gzipped u-boot::
+
+	cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
+
+- Now we've got everything to build android boot image::
 
 	mkbootimg --base 0x0 --kernel_offset 0x00008000 \
 	--ramdisk_offset 0x02000000 --tags_offset 0x01e00000 \
@@ -68,16 +89,69 @@ Now we've got everything to build android boot image:::
 	--kernel u-boot.bin.gz-dtb \
 	-o boot.img
 
-Flash image with your phone's flashing method.
+- Flash image with your phone's flashing method.
 
-Boards
-------------
-starqlte
-^^^^^^^^^^^^
+More information can be found on the `Samsung S9 page`_.
 
-The starqltechn is a production board for Samsung S9 (SM-G9600) phone,
-based on the Qualcomm SDM845 SoC.
+dragonboard845c
+^^^^^^^^^^^^^^^
 
-More information can be found on the `Samsung S9 page`_.
+The dragonboard845c is a Qualcomm Robotics RB3 Development Platform, based on
+the Qualcomm SDM845 SoC.
+
+Steps:
+
+- Build u-boot::
+
+	$ export CROSS_COMPILE=<aarch64 toolchain prefix>
+	$ make dragonboard845c_defconfig
+	$ make
+
+- Create dummy dtb::
+
+	workdir=/tmp/prepare_payload
+	mkdir -p "$workdir"
+	mock_dtb="$workdir"/payload_mock.dtb
+
+	dtc -I dts -O dtb -o "$mock_dtb" << EOF
+	/dts-v1/;
+	/ {
+		#address-cells = <2>;
+		#size-cells = <2>;
+
+		memory@80000000 {
+			device_type = "memory";
+			/* We expect the bootloader to fill in the size */
+			reg = <0 0x80000000 0 0>;
+		};
+
+		chosen { };
+	};
+	EOF
+
+- gzip u-boot::
+
+	gzip u-boot.bin
+
+- Append dtb to gzipped u-boot::
+
+	 cat u-boot.bin.gz "$mock_dtb" > u-boot.bin.gz-dtb
+
+- A ``db845c.its`` file can be found in ``board/qualcomm/dragonboard845c/``
+  directory. It expects a folder as ``db845c_imgs/`` in the main directory
+  containing pre-built kernel, dts and ramdisk images. See ``db845c.its``
+  for full path to images::
+
+	mkimage -f db845c.its db845c.itb
+
+- Now we've got everything to build android boot image::
+
+	mkbootimg --kernel u-boot.bin.gz-dtb --ramdisk db845c.itb \
+	--output boot.img --pagesize 4096 --base 0x80000000
+
+- Flash boot.img using db845c fastboot method.
+
+More information can be found on the `DragonBoard 845c page`_.
 
 .. _Samsung S9 page: https://en.wikipedia.org/wiki/Samsung_Galaxy_S9
+.. _DragonBoard 845c page: https://www.96boards.org/product/rb3-platform/
diff --git a/drivers/dma/ti/Makefile b/drivers/dma/ti/Makefile
index 56f348700d4..6807eb8e8b2 100644
--- a/drivers/dma/ti/Makefile
+++ b/drivers/dma/ti/Makefile
@@ -3,7 +3,7 @@
 obj-$(CONFIG_TI_K3_NAVSS_UDMA) += k3-udma.o
 obj-$(CONFIG_TI_K3_PSIL) += k3-psil-data.o
 k3-psil-data-y += k3-psil.o
-k3-psil-data-$(CONFIG_SOC_K3_AM6) += k3-psil-am654.o
+k3-psil-data-$(CONFIG_SOC_K3_AM654) += k3-psil-am654.o
 k3-psil-data-$(CONFIG_SOC_K3_J721E) += k3-psil-j721e.o
 k3-psil-data-$(CONFIG_SOC_K3_J721S2) += k3-psil-j721s2.o
 k3-psil-data-$(CONFIG_SOC_K3_AM642) += k3-psil-am64.o
diff --git a/drivers/dma/ti/k3-psil.c b/drivers/dma/ti/k3-psil.c
index f1330bf4b03..f23c8ca2b74 100644
--- a/drivers/dma/ti/k3-psil.c
+++ b/drivers/dma/ti/k3-psil.c
@@ -16,7 +16,7 @@ struct psil_endpoint_config *psil_get_ep_config(u32 thread_id)
 	int i;
 
 	if (!soc_ep_map) {
-		if (IS_ENABLED(CONFIG_SOC_K3_AM6))
+		if (IS_ENABLED(CONFIG_SOC_K3_AM654))
 			soc_ep_map = &am654_ep_map;
 		else if (IS_ENABLED(CONFIG_SOC_K3_J721E))
 			soc_ep_map = &j721e_ep_map;
diff --git a/drivers/iommu/apple_dart.c b/drivers/iommu/apple_dart.c
index f2e17009607..2faacb8f3b6 100644
--- a/drivers/iommu/apple_dart.c
+++ b/drivers/iommu/apple_dart.c
@@ -24,6 +24,12 @@
 #define  DART_TTBR_VALID	BIT(31)
 #define  DART_TTBR_SHIFT	12
 
+#define DART_T8110_TCR(sid)	(0x1000 + 4 * (sid))
+#define  DART_T8110_TCR_BYPASS_DAPF		BIT(2)
+#define  DART_T8110_TCR_BYPASS_DART		BIT(1)
+#define  DART_T8110_TCR_TRANSLATE_ENABLE	BIT(0)
+#define DART_T8110_TTBR(sid)	(0x1400 + 4 * (sid))
+
 static int apple_dart_probe(struct udevice *dev)
 {
 	void *base;
@@ -34,7 +40,16 @@ static int apple_dart_probe(struct udevice *dev)
 		return -EINVAL;
 
 	u32 params2 = readl(base + DART_PARAMS2);
-	if (params2 & DART_PARAMS2_BYPASS_SUPPORT) {
+	if (!(params2 & DART_PARAMS2_BYPASS_SUPPORT))
+		return 0;
+
+	if (device_is_compatible(dev, "apple,t8112-dart")) {
+		for (sid = 0; sid < 256; sid++) {
+			writel(DART_T8110_TCR_BYPASS_DART | DART_T8110_TCR_BYPASS_DAPF,
+			       base + DART_T8110_TCR(sid));
+			writel(0, base + DART_T8110_TTBR(sid));
+		}
+	} else {
 		for (sid = 0; sid < 16; sid++) {
 			writel(DART_TCR_BYPASS_DART | DART_TCR_BYPASS_DAPF,
 			       base + DART_TCR(sid));
@@ -49,6 +64,7 @@ static int apple_dart_probe(struct udevice *dev)
 static const struct udevice_id apple_dart_ids[] = {
 	{ .compatible = "apple,t8103-dart" },
 	{ .compatible = "apple,t6000-dart" },
+	{ .compatible = "apple,t8112-dart" },
 	{ /* sentinel */ }
 };
 
diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c
index d63d7b3a2c1..604f9c3ff99 100644
--- a/drivers/mmc/msm_sdhci.c
+++ b/drivers/mmc/msm_sdhci.c
@@ -22,18 +22,17 @@
 #define SDCC_MCI_POWER_SW_RST BIT(7)
 
 /* This is undocumented register */
-#define SDCC_MCI_VERSION             0x50
-#define SDCC_MCI_VERSION_MAJOR_SHIFT 28
-#define SDCC_MCI_VERSION_MAJOR_MASK  (0xf << SDCC_MCI_VERSION_MAJOR_SHIFT)
-#define SDCC_MCI_VERSION_MINOR_MASK  0xff
+#define SDCC_MCI_VERSION		0x50
+#define SDCC_V5_VERSION			0x318
+
+#define SDCC_VERSION_MAJOR_SHIFT	28
+#define SDCC_VERSION_MAJOR_MASK		(0xf << SDCC_VERSION_MAJOR_SHIFT)
+#define SDCC_VERSION_MINOR_MASK		0xff
 
 #define SDCC_MCI_STATUS2 0x6C
 #define SDCC_MCI_STATUS2_MCI_ACT 0x1
 #define SDCC_MCI_HC_MODE 0x78
 
-/* Offset to SDHCI registers */
-#define SDCC_SDHCI_OFFSET 0x900
-
 /* Non standard (?) SDHCI register */
 #define SDHCI_VENDOR_SPEC_CAPABILITIES0  0x11c
 
@@ -47,6 +46,10 @@ struct msm_sdhc {
 	void *base;
 };
 
+struct msm_sdhc_variant_info {
+	bool mci_removed;
+};
+
 DECLARE_GLOBAL_DATA_PTR;
 
 static int msm_sdc_clk_init(struct udevice *dev)
@@ -85,25 +88,8 @@ static int msm_sdc_clk_init(struct udevice *dev)
 	return 0;
 }
 
-static int msm_sdc_probe(struct udevice *dev)
+static int msm_sdc_mci_init(struct msm_sdhc *prv)
 {
-	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
-	struct msm_sdhc_plat *plat = dev_get_plat(dev);
-	struct msm_sdhc *prv = dev_get_priv(dev);
-	struct sdhci_host *host = &prv->host;
-	u32 core_version, core_minor, core_major;
-	u32 caps;
-	int ret;
-
-	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
-
-	host->max_clk = 0;
-
-	/* Init clocks */
-	ret = msm_sdc_clk_init(dev);
-	if (ret)
-		return ret;
-
 	/* Reset the core and Enable SDHC mode */
 	writel(readl(prv->base + SDCC_MCI_POWER) | SDCC_MCI_POWER_SW_RST,
 	       prv->base + SDCC_MCI_POWER);
@@ -126,12 +112,45 @@ static int msm_sdc_probe(struct udevice *dev)
 	/* Enable host-controller mode */
 	writel(1, prv->base + SDCC_MCI_HC_MODE);
 
-	core_version = readl(prv->base + SDCC_MCI_VERSION);
+	return 0;
+}
 
-	core_major = (core_version & SDCC_MCI_VERSION_MAJOR_MASK);
-	core_major >>= SDCC_MCI_VERSION_MAJOR_SHIFT;
+static int msm_sdc_probe(struct udevice *dev)
+{
+	struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
+	struct msm_sdhc_plat *plat = dev_get_plat(dev);
+	struct msm_sdhc *prv = dev_get_priv(dev);
+	const struct msm_sdhc_variant_info *var_info;
+	struct sdhci_host *host = &prv->host;
+	u32 core_version, core_minor, core_major;
+	u32 caps;
+	int ret;
 
-	core_minor = core_version & SDCC_MCI_VERSION_MINOR_MASK;
+	host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD | SDHCI_QUIRK_BROKEN_R1B;
+
+	host->max_clk = 0;
+
+	/* Init clocks */
+	ret = msm_sdc_clk_init(dev);
+	if (ret)
+		return ret;
+
+	var_info = (void *)dev_get_driver_data(dev);
+	if (!var_info->mci_removed) {
+		ret = msm_sdc_mci_init(prv);
+		if (ret)
+			return ret;
+	}
+
+	if (!var_info->mci_removed)
+		core_version = readl(prv->base + SDCC_MCI_VERSION);
+	else
+		core_version = readl(host->ioaddr + SDCC_V5_VERSION);
+
+	core_major = (core_version & SDCC_VERSION_MAJOR_MASK);
+	core_major >>= SDCC_VERSION_MAJOR_SHIFT;
+
+	core_minor = core_version & SDCC_VERSION_MINOR_MASK;
 
 	/*
 	 * Support for some capabilities is not advertised by newer
@@ -161,9 +180,13 @@ static int msm_sdc_probe(struct udevice *dev)
 static int msm_sdc_remove(struct udevice *dev)
 {
 	struct msm_sdhc *priv = dev_get_priv(dev);
+	const struct msm_sdhc_variant_info *var_info;
+
+	var_info = (void *)dev_get_driver_data(dev);
 
-	 /* Disable host-controller mode */
-	writel(0, priv->base + SDCC_MCI_HC_MODE);
+	/* Disable host-controller mode */
+	if (!var_info->mci_removed)
+		writel(0, priv->base + SDCC_MCI_HC_MODE);
 
 	return 0;
 }
@@ -195,8 +218,17 @@ static int msm_sdc_bind(struct udevice *dev)
 	return sdhci_bind(dev, &plat->mmc, &plat->cfg);
 }
 
+static const struct msm_sdhc_variant_info msm_sdhc_mci_var = {
+	.mci_removed = false,
+};
+
+static const struct msm_sdhc_variant_info msm_sdhc_v5_var = {
+	.mci_removed = true,
+};
+
 static const struct udevice_id msm_mmc_ids[] = {
-	{ .compatible = "qcom,sdhci-msm-v4" },
+	{ .compatible = "qcom,sdhci-msm-v4", .data = (ulong)&msm_sdhc_mci_var },
+	{ .compatible = "qcom,sdhci-msm-v5", .data = (ulong)&msm_sdhc_v5_var },
 	{ }
 };
 
diff --git a/drivers/phy/ti/phy-j721e-wiz.c b/drivers/phy/ti/phy-j721e-wiz.c
index 686cdc6f7c2..fb6b6cf3fff 100644
--- a/drivers/phy/ti/phy-j721e-wiz.c
+++ b/drivers/phy/ti/phy-j721e-wiz.c
@@ -221,6 +221,44 @@ enum wiz_type {
 	AM64_WIZ_10G,
 };
 
+struct wiz_data {
+	enum wiz_type type;
+	const struct reg_field *pll0_refclk_mux_sel;
+	const struct reg_field *pll1_refclk_mux_sel;
+	const struct reg_field *refclk_dig_sel;
+	const struct reg_field *pma_cmn_refclk1_dig_div;
+	const struct wiz_clk_mux_sel *clk_mux_sel;
+	unsigned int clk_div_sel_num;
+};
+
+static const struct wiz_data j721e_16g_data = {
+	.type = J721E_WIZ_16G,
+	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+	.refclk_dig_sel = &refclk_dig_sel_16g,
+	.pma_cmn_refclk1_dig_div = &pma_cmn_refclk1_dig_div,
+	.clk_mux_sel = clk_mux_sel_16g,
+	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G,
+};
+
+static const struct wiz_data j721e_10g_data = {
+	.type = J721E_WIZ_10G,
+	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+	.refclk_dig_sel = &refclk_dig_sel_10g,
+	.clk_mux_sel = clk_mux_sel_10g,
+	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
+static struct wiz_data am64_10g_data = {
+	.type = AM64_WIZ_10G,
+	.pll0_refclk_mux_sel = &pll0_refclk_mux_sel,
+	.pll1_refclk_mux_sel = &pll1_refclk_mux_sel,
+	.refclk_dig_sel = &refclk_dig_sel_10g,
+	.clk_mux_sel = clk_mux_sel_10g,
+	.clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G,
+};
+
 #define WIZ_TYPEC_DIR_DEBOUNCE_MIN	100	/* ms */
 #define WIZ_TYPEC_DIR_DEBOUNCE_MAX	1000
 
@@ -253,6 +291,7 @@ struct wiz {
 	u32			lane_phy_type[WIZ_MAX_LANES];
 	struct clk		*input_clks[WIZ_MAX_INPUT_CLOCKS];
 	unsigned int		id;
+	const struct wiz_data	*data;
 };
 
 struct wiz_div_clk {
@@ -667,7 +706,7 @@ static int wiz_regfield_init(struct wiz *wiz)
 	struct regmap *regmap = wiz->regmap;
 	int num_lanes = wiz->num_lanes;
 	struct udevice *dev = wiz->dev;
-	enum wiz_type type;
+	const struct wiz_data *data = wiz->data;
 	int i;
 
 	wiz->por_en = devm_regmap_field_alloc(dev, regmap, por_en);
@@ -704,36 +743,31 @@ static int wiz_regfield_init(struct wiz *wiz)
 		return PTR_ERR(wiz->div_sel_field[CMN_REFCLK]);
 	}
 
-	wiz->div_sel_field[CMN_REFCLK1] =
-		devm_regmap_field_alloc(dev, regmap, pma_cmn_refclk1_dig_div);
-	if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
-		dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
-		return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
+	if (data->pma_cmn_refclk1_dig_div) {
+		wiz->div_sel_field[CMN_REFCLK1] =
+			devm_regmap_field_alloc(dev, regmap, *data->pma_cmn_refclk1_dig_div);
+		if (IS_ERR(wiz->div_sel_field[CMN_REFCLK1])) {
+			dev_err(dev, "PMA_CMN_REFCLK1_DIG_DIV reg field init failed\n");
+			return PTR_ERR(wiz->div_sel_field[CMN_REFCLK1]);
+		}
 	}
 
 	wiz->mux_sel_field[PLL0_REFCLK] =
-		devm_regmap_field_alloc(dev, regmap, pll0_refclk_mux_sel);
+		devm_regmap_field_alloc(dev, regmap, *data->pll0_refclk_mux_sel);
 	if (IS_ERR(wiz->mux_sel_field[PLL0_REFCLK])) {
 		dev_err(dev, "PLL0_REFCLK_SEL reg field init failed\n");
 		return PTR_ERR(wiz->mux_sel_field[PLL0_REFCLK]);
 	}
 
 	wiz->mux_sel_field[PLL1_REFCLK] =
-		devm_regmap_field_alloc(dev, regmap, pll1_refclk_mux_sel);
+		devm_regmap_field_alloc(dev, regmap, *data->pll1_refclk_mux_sel);
 	if (IS_ERR(wiz->mux_sel_field[PLL1_REFCLK])) {
 		dev_err(dev, "PLL1_REFCLK_SEL reg field init failed\n");
 		return PTR_ERR(wiz->mux_sel_field[PLL1_REFCLK]);
 	}
 
-	type = dev_get_driver_data(dev);
-	if (type == J721E_WIZ_10G || type == AM64_WIZ_10G)
-		wiz->mux_sel_field[REFCLK_DIG] =
-			devm_regmap_field_alloc(dev, regmap,
-						refclk_dig_sel_10g);
-	else
-		wiz->mux_sel_field[REFCLK_DIG] =
-			devm_regmap_field_alloc(dev, regmap,
-						refclk_dig_sel_16g);
+	wiz->mux_sel_field[REFCLK_DIG] =
+		devm_regmap_field_alloc(dev, regmap, *data->refclk_dig_sel);
 	if (IS_ERR(wiz->mux_sel_field[REFCLK_DIG])) {
 		dev_err(dev, "REFCLK_DIG_SEL reg field init failed\n");
 		return PTR_ERR(wiz->mux_sel_field[REFCLK_DIG]);
@@ -1059,14 +1093,12 @@ static int j721e_wiz_probe(struct udevice *dev)
 	wiz->num_lanes = num_lanes;
 	wiz->dev = dev;
 	wiz->clk_div_sel = clk_div_sel;
-	wiz->type = dev_get_driver_data(dev);
-	if (wiz->type == J721E_WIZ_10G || wiz->type == AM64_WIZ_10G) {
-		wiz->clk_mux_sel = clk_mux_sel_10g;
-		wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_10G;
-	} else {
-		wiz->clk_mux_sel = clk_mux_sel_16g;
-		wiz->clk_div_sel_num = WIZ_DIV_NUM_CLOCKS_16G;
-	}
+
+	wiz->data = (struct wiz_data *)dev_get_driver_data(dev);
+	wiz->type = wiz->data->type;
+
+	wiz->clk_mux_sel = (struct wiz_clk_mux_sel *)wiz->data->clk_mux_sel;
+	wiz->clk_div_sel_num = wiz->data->clk_div_sel_num;
 
 	rc = wiz_get_lane_phy_types(dev, wiz);
 	if (rc) {
@@ -1133,13 +1165,13 @@ static int j721e_wiz_remove(struct udevice *dev)
 
 static const struct udevice_id j721e_wiz_ids[] = {
 	{
-		.compatible = "ti,j721e-wiz-16g", .data = J721E_WIZ_16G,
+		.compatible = "ti,j721e-wiz-16g", .data = (ulong)&j721e_16g_data,
 	},
 	{
-		.compatible = "ti,j721e-wiz-10g", .data = J721E_WIZ_10G,
+		.compatible = "ti,j721e-wiz-10g", .data = (ulong)&j721e_10g_data,
 	},
 	{
-		.compatible = "ti,am64-wiz-10g", .data = AM64_WIZ_10G,
+		.compatible = "ti,am64-wiz-10g", .data = (ulong)&am64_10g_data,
 	},
 	{}
 };
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 7c346180bae..86857c06272 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -45,7 +45,7 @@ config MPC83XX_SDRAM
 
 config K3_AM654_DDRSS
 	bool "Enable AM654 DDRSS support"
-	depends on RAM && SOC_K3_AM6
+	depends on RAM && SOC_K3_AM654
 	help
 	  K3 based AM654 devices has DDR memory subsystem that comprises
 	  Synopys DDR controller, Synopsis DDR phy and wrapper logic to
diff --git a/drivers/xen/hypervisor.c b/drivers/xen/hypervisor.c
index 25608948323..16c7c96c94e 100644
--- a/drivers/xen/hypervisor.c
+++ b/drivers/xen/hypervisor.c
@@ -144,6 +144,36 @@ struct shared_info *map_shared_info(void *p)
 	return HYPERVISOR_shared_info;
 }
 
+void unmap_shared_info(void)
+{
+	xen_pfn_t shared_info_pfn = virt_to_pfn(HYPERVISOR_shared_info);
+	struct xen_remove_from_physmap xrfp = {0};
+	struct xen_memory_reservation reservation = {0};
+	xen_ulong_t nr_exts = 1;
+
+	xrfp.domid = DOMID_SELF;
+	xrfp.gpfn = shared_info_pfn;
+	if (HYPERVISOR_memory_op(XENMEM_remove_from_physmap, &xrfp) != 0)
+		panic("Failed to unmap HYPERVISOR_shared_info\n");
+
+	/*
+	 * After removing from physmap there will be a hole in address space on
+	 * HYPERVISOR_shared_info address, so to free memory allocated with
+	 * memalign and prevent exceptions during access to this page we need to
+	 * fill this 4KB hole with XENMEM_populate_physmap before jumping to Linux.
+	 */
+	reservation.domid = DOMID_SELF;
+	reservation.extent_order = 0;
+	reservation.address_bits = 0;
+	set_xen_guest_handle(reservation.extent_start, &shared_info_pfn);
+	reservation.nr_extents = nr_exts;
+	if (HYPERVISOR_memory_op(XENMEM_populate_physmap, &reservation) != nr_exts)
+		panic("Failed to populate memory on HYPERVISOR_shared_info addr\n");
+
+	/* Now we can return this to memory allocator */
+	free(HYPERVISOR_shared_info);
+}
+
 void do_hypervisor_callback(struct pt_regs *regs)
 {
 	unsigned long l1, l2, l1i, l2i;
@@ -251,4 +281,5 @@ void xen_fini(void)
 	fini_gnttab();
 	fini_xenbus();
 	fini_events();
+	unmap_shared_info();
 }
diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h
new file mode 100644
index 00000000000..677a4856230
--- /dev/null
+++ b/include/configs/dragonboard845c.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#ifndef __CONFIGS_SDM845_H
+#define __CONFIGS_SDM845_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-sdm845.h>
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootm_size=0x5000000\0"	\
+	"bootm_low=0x80000000\0"	\
+	"bootcmd=bootm $prevbl_initrd_start_addr\0"
+
+#endif
diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h
new file mode 100644
index 00000000000..58020ae95b1
--- /dev/null
+++ b/include/configs/qcs404-evb.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Configuration file for QCS404 evaluation board
+ *
+ * (C) Copyright 2022 Sumit Garg <sumit.garg@linaro.org>
+ */
+
+#ifndef __CONFIGS_QCS404EVB_H
+#define __CONFIGS_QCS404EVB_H
+
+#include <linux/sizes.h>
+#include <asm/arch/sysmap-qcs404.h>
+
+#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200, 230400, 460800, 921600 }
+
+#define CONFIG_EXTRA_ENV_SETTINGS \
+	"bootm_size=0x5000000\0"	\
+	"bootm_low=0x80000000\0"	\
+	"bootcmd=bootm $prevbl_initrd_start_addr\0"
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-qcs404.h b/include/dt-bindings/clock/qcom,gcc-qcs404.h
new file mode 100644
index 00000000000..bc305154334
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-qcs404.h
@@ -0,0 +1,180 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+#define _DT_BINDINGS_CLK_QCOM_GCC_QCS404_H
+
+#define GCC_APSS_AHB_CLK_SRC				0
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK_SRC			1
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK_SRC			2
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK_SRC			3
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK_SRC			4
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK_SRC			5
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK_SRC			6
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK_SRC			7
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK_SRC			8
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK_SRC			9
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK_SRC			10
+#define GCC_BLSP1_UART0_APPS_CLK_SRC			11
+#define GCC_BLSP1_UART1_APPS_CLK_SRC			12
+#define GCC_BLSP1_UART2_APPS_CLK_SRC			13
+#define GCC_BLSP1_UART3_APPS_CLK_SRC			14
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK_SRC			15
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK_SRC			16
+#define GCC_BLSP2_UART0_APPS_CLK_SRC			17
+#define GCC_BYTE0_CLK_SRC				18
+#define GCC_EMAC_CLK_SRC				19
+#define GCC_EMAC_PTP_CLK_SRC				20
+#define GCC_ESC0_CLK_SRC				21
+#define GCC_APSS_AHB_CLK				22
+#define GCC_APSS_AXI_CLK				23
+#define GCC_BIMC_APSS_AXI_CLK				24
+#define GCC_BIMC_GFX_CLK				25
+#define GCC_BIMC_MDSS_CLK				26
+#define GCC_BLSP1_AHB_CLK				27
+#define GCC_BLSP1_QUP0_I2C_APPS_CLK			28
+#define GCC_BLSP1_QUP0_SPI_APPS_CLK			29
+#define GCC_BLSP1_QUP1_I2C_APPS_CLK			30
+#define GCC_BLSP1_QUP1_SPI_APPS_CLK			31
+#define GCC_BLSP1_QUP2_I2C_APPS_CLK			32
+#define GCC_BLSP1_QUP2_SPI_APPS_CLK			33
+#define GCC_BLSP1_QUP3_I2C_APPS_CLK			34
+#define GCC_BLSP1_QUP3_SPI_APPS_CLK			35
+#define GCC_BLSP1_QUP4_I2C_APPS_CLK			36
+#define GCC_BLSP1_QUP4_SPI_APPS_CLK			37
+#define GCC_BLSP1_UART0_APPS_CLK			38
+#define GCC_BLSP1_UART1_APPS_CLK			39
+#define GCC_BLSP1_UART2_APPS_CLK			40
+#define GCC_BLSP1_UART3_APPS_CLK			41
+#define GCC_BLSP2_AHB_CLK				42
+#define GCC_BLSP2_QUP0_I2C_APPS_CLK			43
+#define GCC_BLSP2_QUP0_SPI_APPS_CLK			44
+#define GCC_BLSP2_UART0_APPS_CLK			45
+#define GCC_BOOT_ROM_AHB_CLK				46
+#define GCC_DCC_CLK					47
+#define GCC_GENI_IR_H_CLK				48
+#define GCC_ETH_AXI_CLK					49
+#define GCC_ETH_PTP_CLK					50
+#define GCC_ETH_RGMII_CLK				51
+#define GCC_ETH_SLAVE_AHB_CLK				52
+#define GCC_GENI_IR_S_CLK				53
+#define GCC_GP1_CLK					54
+#define GCC_GP2_CLK					55
+#define GCC_GP3_CLK					56
+#define GCC_MDSS_AHB_CLK				57
+#define GCC_MDSS_AXI_CLK				58
+#define GCC_MDSS_BYTE0_CLK				59
+#define GCC_MDSS_ESC0_CLK				60
+#define GCC_MDSS_HDMI_APP_CLK				61
+#define GCC_MDSS_HDMI_PCLK_CLK				62
+#define GCC_MDSS_MDP_CLK				63
+#define GCC_MDSS_PCLK0_CLK				64
+#define GCC_MDSS_VSYNC_CLK				65
+#define GCC_OXILI_AHB_CLK				66
+#define GCC_OXILI_GFX3D_CLK				67
+#define GCC_PCIE_0_AUX_CLK				68
+#define GCC_PCIE_0_CFG_AHB_CLK				69
+#define GCC_PCIE_0_MSTR_AXI_CLK				70
+#define GCC_PCIE_0_PIPE_CLK				71
+#define GCC_PCIE_0_SLV_AXI_CLK				72
+#define GCC_PCNOC_USB2_CLK				73
+#define GCC_PCNOC_USB3_CLK				74
+#define GCC_PDM2_CLK					75
+#define GCC_PDM_AHB_CLK					76
+#define GCC_VSYNC_CLK_SRC				77
+#define GCC_PRNG_AHB_CLK				78
+#define GCC_PWM0_XO512_CLK				79
+#define GCC_PWM1_XO512_CLK				80
+#define GCC_PWM2_XO512_CLK				81
+#define GCC_SDCC1_AHB_CLK				82
+#define GCC_SDCC1_APPS_CLK				83
+#define GCC_SDCC1_ICE_CORE_CLK				84
+#define GCC_SDCC2_AHB_CLK				85
+#define GCC_SDCC2_APPS_CLK				86
+#define GCC_SYS_NOC_USB3_CLK				87
+#define GCC_USB20_MOCK_UTMI_CLK				88
+#define GCC_USB2A_PHY_SLEEP_CLK				89
+#define GCC_USB30_MASTER_CLK				90
+#define GCC_USB30_MOCK_UTMI_CLK				91
+#define GCC_USB30_SLEEP_CLK				92
+#define GCC_USB3_PHY_AUX_CLK				93
+#define GCC_USB3_PHY_PIPE_CLK				94
+#define GCC_USB_HS_PHY_CFG_AHB_CLK			95
+#define GCC_USB_HS_SYSTEM_CLK				96
+#define GCC_GFX3D_CLK_SRC				97
+#define GCC_GP1_CLK_SRC					98
+#define GCC_GP2_CLK_SRC					99
+#define GCC_GP3_CLK_SRC					100
+#define GCC_GPLL0_OUT_MAIN				101
+#define GCC_GPLL1_OUT_MAIN				102
+#define GCC_GPLL3_OUT_MAIN				103
+#define GCC_GPLL4_OUT_MAIN				104
+#define GCC_HDMI_APP_CLK_SRC				105
+#define GCC_HDMI_PCLK_CLK_SRC				106
+#define GCC_MDP_CLK_SRC					107
+#define GCC_PCIE_0_AUX_CLK_SRC				108
+#define GCC_PCIE_0_PIPE_CLK_SRC				109
+#define GCC_PCLK0_CLK_SRC				110
+#define GCC_PDM2_CLK_SRC				111
+#define GCC_SDCC1_APPS_CLK_SRC				112
+#define GCC_SDCC1_ICE_CORE_CLK_SRC			113
+#define GCC_SDCC2_APPS_CLK_SRC				114
+#define GCC_USB20_MOCK_UTMI_CLK_SRC			115
+#define GCC_USB30_MASTER_CLK_SRC			116
+#define GCC_USB30_MOCK_UTMI_CLK_SRC			117
+#define GCC_USB3_PHY_AUX_CLK_SRC			118
+#define GCC_USB_HS_SYSTEM_CLK_SRC			119
+#define GCC_GPLL0_AO_CLK_SRC				120
+#define GCC_USB_HS_INACTIVITY_TIMERS_CLK		122
+#define GCC_GPLL0_AO_OUT_MAIN				123
+#define GCC_GPLL0_SLEEP_CLK_SRC				124
+#define GCC_GPLL6					125
+#define GCC_GPLL6_OUT_AUX				126
+#define GCC_MDSS_MDP_VOTE_CLK				127
+#define GCC_MDSS_ROTATOR_VOTE_CLK			128
+#define GCC_BIMC_GPU_CLK				129
+#define GCC_GTCU_AHB_CLK				130
+#define GCC_GFX_TCU_CLK					131
+#define GCC_GFX_TBU_CLK					132
+#define GCC_SMMU_CFG_CLK				133
+#define GCC_APSS_TCU_CLK				134
+#define GCC_CRYPTO_AHB_CLK				135
+#define GCC_CRYPTO_AXI_CLK				136
+#define GCC_CRYPTO_CLK					137
+#define GCC_MDP_TBU_CLK					138
+#define GCC_QDSS_DAP_CLK				139
+#define GCC_DCC_XO_CLK					140
+#define GCC_WCSS_Q6_AHB_CLK				141
+#define GCC_WCSS_Q6_AXIM_CLK				142
+#define GCC_CDSP_CFG_AHB_CLK				143
+#define GCC_BIMC_CDSP_CLK				144
+#define GCC_CDSP_TBU_CLK				145
+#define GCC_CDSP_BIMC_CLK_SRC				146
+
+#define GCC_GENI_IR_BCR					0
+#define GCC_USB_HS_BCR					1
+#define GCC_USB2_HS_PHY_ONLY_BCR			2
+#define GCC_QUSB2_PHY_BCR				3
+#define GCC_USB_HS_PHY_CFG_AHB_BCR			4
+#define GCC_USB2A_PHY_BCR				5
+#define GCC_USB3_PHY_BCR				6
+#define GCC_USB_30_BCR					7
+#define GCC_USB3PHY_PHY_BCR				8
+#define GCC_PCIE_0_BCR					9
+#define GCC_PCIE_0_PHY_BCR				10
+#define GCC_PCIE_0_LINK_DOWN_BCR			11
+#define GCC_PCIEPHY_0_PHY_BCR				12
+#define GCC_EMAC_BCR					13
+#define GCC_CDSP_RESTART				14
+#define GCC_PCIE_0_AXI_MASTER_STICKY_ARES		15
+#define GCC_PCIE_0_AHB_ARES				16
+#define GCC_PCIE_0_AXI_SLAVE_ARES			17
+#define GCC_PCIE_0_AXI_MASTER_ARES			18
+#define GCC_PCIE_0_CORE_STICKY_ARES			19
+#define GCC_PCIE_0_SLEEP_ARES				20
+#define GCC_PCIE_0_PIPE_ARES				21
+#define GCC_WDSP_RESTART				22
+
+#endif
diff --git a/include/dt-bindings/clock/qcom,gcc-sdm845.h b/include/dt-bindings/clock/qcom,gcc-sdm845.h
new file mode 100644
index 00000000000..968fa65b9c4
--- /dev/null
+++ b/include/dt-bindings/clock/qcom,gcc-sdm845.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (c) 2018, The Linux Foundation. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+#define _DT_BINDINGS_CLK_SDM_GCC_SDM845_H
+
+/* GCC clock registers */
+#define GCC_AGGRE_NOC_PCIE_TBU_CLK				0
+#define GCC_AGGRE_UFS_CARD_AXI_CLK				1
+#define GCC_AGGRE_UFS_PHY_AXI_CLK				2
+#define GCC_AGGRE_USB3_PRIM_AXI_CLK				3
+#define GCC_AGGRE_USB3_SEC_AXI_CLK				4
+#define GCC_BOOT_ROM_AHB_CLK					5
+#define GCC_CAMERA_AHB_CLK					6
+#define GCC_CAMERA_AXI_CLK					7
+#define GCC_CAMERA_XO_CLK					8
+#define GCC_CE1_AHB_CLK						9
+#define GCC_CE1_AXI_CLK						10
+#define GCC_CE1_CLK						11
+#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK				12
+#define GCC_CFG_NOC_USB3_SEC_AXI_CLK				13
+#define GCC_CPUSS_AHB_CLK					14
+#define GCC_CPUSS_AHB_CLK_SRC					15
+#define GCC_CPUSS_RBCPR_CLK					16
+#define GCC_CPUSS_RBCPR_CLK_SRC					17
+#define GCC_DDRSS_GPU_AXI_CLK					18
+#define GCC_DISP_AHB_CLK					19
+#define GCC_DISP_AXI_CLK					20
+#define GCC_DISP_GPLL0_CLK_SRC					21
+#define GCC_DISP_GPLL0_DIV_CLK_SRC				22
+#define GCC_DISP_XO_CLK						23
+#define GCC_GP1_CLK						24
+#define GCC_GP1_CLK_SRC						25
+#define GCC_GP2_CLK						26
+#define GCC_GP2_CLK_SRC						27
+#define GCC_GP3_CLK						28
+#define GCC_GP3_CLK_SRC						29
+#define GCC_GPU_CFG_AHB_CLK					30
+#define GCC_GPU_GPLL0_CLK_SRC					31
+#define GCC_GPU_GPLL0_DIV_CLK_SRC				32
+#define GCC_GPU_MEMNOC_GFX_CLK					33
+#define GCC_GPU_SNOC_DVM_GFX_CLK				34
+#define GCC_MSS_AXIS2_CLK					35
+#define GCC_MSS_CFG_AHB_CLK					36
+#define GCC_MSS_GPLL0_DIV_CLK_SRC				37
+#define GCC_MSS_MFAB_AXIS_CLK					38
+#define GCC_MSS_Q6_MEMNOC_AXI_CLK				39
+#define GCC_MSS_SNOC_AXI_CLK					40
+#define GCC_PCIE_0_AUX_CLK					41
+#define GCC_PCIE_0_AUX_CLK_SRC					42
+#define GCC_PCIE_0_CFG_AHB_CLK					43
+#define GCC_PCIE_0_CLKREF_CLK					44
+#define GCC_PCIE_0_MSTR_AXI_CLK					45
+#define GCC_PCIE_0_PIPE_CLK					46
+#define GCC_PCIE_0_SLV_AXI_CLK					47
+#define GCC_PCIE_0_SLV_Q2A_AXI_CLK				48
+#define GCC_PCIE_1_AUX_CLK					49
+#define GCC_PCIE_1_AUX_CLK_SRC					50
+#define GCC_PCIE_1_CFG_AHB_CLK					51
+#define GCC_PCIE_1_CLKREF_CLK					52
+#define GCC_PCIE_1_MSTR_AXI_CLK					53
+#define GCC_PCIE_1_PIPE_CLK					54
+#define GCC_PCIE_1_SLV_AXI_CLK					55
+#define GCC_PCIE_1_SLV_Q2A_AXI_CLK				56
+#define GCC_PCIE_PHY_AUX_CLK					57
+#define GCC_PCIE_PHY_REFGEN_CLK					58
+#define GCC_PCIE_PHY_REFGEN_CLK_SRC				59
+#define GCC_PDM2_CLK						60
+#define GCC_PDM2_CLK_SRC					61
+#define GCC_PDM_AHB_CLK						62
+#define GCC_PDM_XO4_CLK						63
+#define GCC_PRNG_AHB_CLK					64
+#define GCC_QMIP_CAMERA_AHB_CLK					65
+#define GCC_QMIP_DISP_AHB_CLK					66
+#define GCC_QMIP_VIDEO_AHB_CLK					67
+#define GCC_QUPV3_WRAP0_S0_CLK					68
+#define GCC_QUPV3_WRAP0_S0_CLK_SRC				69
+#define GCC_QUPV3_WRAP0_S1_CLK					70
+#define GCC_QUPV3_WRAP0_S1_CLK_SRC				71
+#define GCC_QUPV3_WRAP0_S2_CLK					72
+#define GCC_QUPV3_WRAP0_S2_CLK_SRC				73
+#define GCC_QUPV3_WRAP0_S3_CLK					74
+#define GCC_QUPV3_WRAP0_S3_CLK_SRC				75
+#define GCC_QUPV3_WRAP0_S4_CLK					76
+#define GCC_QUPV3_WRAP0_S4_CLK_SRC				77
+#define GCC_QUPV3_WRAP0_S5_CLK					78
+#define GCC_QUPV3_WRAP0_S5_CLK_SRC				79
+#define GCC_QUPV3_WRAP0_S6_CLK					80
+#define GCC_QUPV3_WRAP0_S6_CLK_SRC				81
+#define GCC_QUPV3_WRAP0_S7_CLK					82
+#define GCC_QUPV3_WRAP0_S7_CLK_SRC				83
+#define GCC_QUPV3_WRAP1_S0_CLK					84
+#define GCC_QUPV3_WRAP1_S0_CLK_SRC				85
+#define GCC_QUPV3_WRAP1_S1_CLK					86
+#define GCC_QUPV3_WRAP1_S1_CLK_SRC				87
+#define GCC_QUPV3_WRAP1_S2_CLK					88
+#define GCC_QUPV3_WRAP1_S2_CLK_SRC				89
+#define GCC_QUPV3_WRAP1_S3_CLK					90
+#define GCC_QUPV3_WRAP1_S3_CLK_SRC				91
+#define GCC_QUPV3_WRAP1_S4_CLK					92
+#define GCC_QUPV3_WRAP1_S4_CLK_SRC				93
+#define GCC_QUPV3_WRAP1_S5_CLK					94
+#define GCC_QUPV3_WRAP1_S5_CLK_SRC				95
+#define GCC_QUPV3_WRAP1_S6_CLK					96
+#define GCC_QUPV3_WRAP1_S6_CLK_SRC				97
+#define GCC_QUPV3_WRAP1_S7_CLK					98
+#define GCC_QUPV3_WRAP1_S7_CLK_SRC				99
+#define GCC_QUPV3_WRAP_0_M_AHB_CLK				100
+#define GCC_QUPV3_WRAP_0_S_AHB_CLK				101
+#define GCC_QUPV3_WRAP_1_M_AHB_CLK				102
+#define GCC_QUPV3_WRAP_1_S_AHB_CLK				103
+#define GCC_SDCC2_AHB_CLK					104
+#define GCC_SDCC2_APPS_CLK					105
+#define GCC_SDCC2_APPS_CLK_SRC					106
+#define GCC_SDCC4_AHB_CLK					107
+#define GCC_SDCC4_APPS_CLK					108
+#define GCC_SDCC4_APPS_CLK_SRC					109
+#define GCC_SYS_NOC_CPUSS_AHB_CLK				110
+#define GCC_TSIF_AHB_CLK					111
+#define GCC_TSIF_INACTIVITY_TIMERS_CLK				112
+#define GCC_TSIF_REF_CLK					113
+#define GCC_TSIF_REF_CLK_SRC					114
+#define GCC_UFS_CARD_AHB_CLK					115
+#define GCC_UFS_CARD_AXI_CLK					116
+#define GCC_UFS_CARD_AXI_CLK_SRC				117
+#define GCC_UFS_CARD_CLKREF_CLK					118
+#define GCC_UFS_CARD_ICE_CORE_CLK				119
+#define GCC_UFS_CARD_ICE_CORE_CLK_SRC				120
+#define GCC_UFS_CARD_PHY_AUX_CLK				121
+#define GCC_UFS_CARD_PHY_AUX_CLK_SRC				122
+#define GCC_UFS_CARD_RX_SYMBOL_0_CLK				123
+#define GCC_UFS_CARD_RX_SYMBOL_1_CLK				124
+#define GCC_UFS_CARD_TX_SYMBOL_0_CLK				125
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK				126
+#define GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC			127
+#define GCC_UFS_MEM_CLKREF_CLK					128
+#define GCC_UFS_PHY_AHB_CLK					129
+#define GCC_UFS_PHY_AXI_CLK					130
+#define GCC_UFS_PHY_AXI_CLK_SRC					131
+#define GCC_UFS_PHY_ICE_CORE_CLK				132
+#define GCC_UFS_PHY_ICE_CORE_CLK_SRC				133
+#define GCC_UFS_PHY_PHY_AUX_CLK					134
+#define GCC_UFS_PHY_PHY_AUX_CLK_SRC				135
+#define GCC_UFS_PHY_RX_SYMBOL_0_CLK				136
+#define GCC_UFS_PHY_RX_SYMBOL_1_CLK				137
+#define GCC_UFS_PHY_TX_SYMBOL_0_CLK				138
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK				139
+#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC				140
+#define GCC_USB30_PRIM_MASTER_CLK				141
+#define GCC_USB30_PRIM_MASTER_CLK_SRC				142
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK				143
+#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC			144
+#define GCC_USB30_PRIM_SLEEP_CLK				145
+#define GCC_USB30_SEC_MASTER_CLK				146
+#define GCC_USB30_SEC_MASTER_CLK_SRC				147
+#define GCC_USB30_SEC_MOCK_UTMI_CLK				148
+#define GCC_USB30_SEC_MOCK_UTMI_CLK_SRC				149
+#define GCC_USB30_SEC_SLEEP_CLK					150
+#define GCC_USB3_PRIM_CLKREF_CLK				151
+#define GCC_USB3_PRIM_PHY_AUX_CLK				152
+#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC				153
+#define GCC_USB3_PRIM_PHY_COM_AUX_CLK				154
+#define GCC_USB3_PRIM_PHY_PIPE_CLK				155
+#define GCC_USB3_SEC_CLKREF_CLK					156
+#define GCC_USB3_SEC_PHY_AUX_CLK				157
+#define GCC_USB3_SEC_PHY_AUX_CLK_SRC				158
+#define GCC_USB3_SEC_PHY_PIPE_CLK				159
+#define GCC_USB3_SEC_PHY_COM_AUX_CLK				160
+#define GCC_USB_PHY_CFG_AHB2PHY_CLK				161
+#define GCC_VIDEO_AHB_CLK					162
+#define GCC_VIDEO_AXI_CLK					163
+#define GCC_VIDEO_XO_CLK					164
+#define GPLL0							165
+#define GPLL0_OUT_EVEN						166
+#define GPLL0_OUT_MAIN						167
+#define GCC_GPU_IREF_CLK					168
+#define GCC_SDCC1_AHB_CLK					169
+#define GCC_SDCC1_APPS_CLK					170
+#define GCC_SDCC1_ICE_CORE_CLK					171
+#define GCC_SDCC1_APPS_CLK_SRC					172
+#define GCC_SDCC1_ICE_CORE_CLK_SRC				173
+#define GCC_APC_VS_CLK						174
+#define GCC_GPU_VS_CLK						175
+#define GCC_MSS_VS_CLK						176
+#define GCC_VDDA_VS_CLK						177
+#define GCC_VDDCX_VS_CLK					178
+#define GCC_VDDMX_VS_CLK					179
+#define GCC_VS_CTRL_AHB_CLK					180
+#define GCC_VS_CTRL_CLK						181
+#define GCC_VS_CTRL_CLK_SRC					182
+#define GCC_VSENSOR_CLK_SRC					183
+#define GPLL4							184
+#define GCC_CPUSS_DVM_BUS_CLK					185
+#define GCC_CPUSS_GNOC_CLK					186
+#define GCC_QSPI_CORE_CLK_SRC					187
+#define GCC_QSPI_CORE_CLK					188
+#define GCC_QSPI_CNOC_PERIPH_AHB_CLK				189
+#define GCC_LPASS_Q6_AXI_CLK					190
+#define GCC_LPASS_SWAY_CLK					191
+
+/* GCC Resets */
+#define GCC_MMSS_BCR						0
+#define GCC_PCIE_0_BCR						1
+#define GCC_PCIE_1_BCR						2
+#define GCC_PCIE_PHY_BCR					3
+#define GCC_PDM_BCR						4
+#define GCC_PRNG_BCR						5
+#define GCC_QUPV3_WRAPPER_0_BCR					6
+#define GCC_QUPV3_WRAPPER_1_BCR					7
+#define GCC_QUSB2PHY_PRIM_BCR					8
+#define GCC_QUSB2PHY_SEC_BCR					9
+#define GCC_SDCC2_BCR						10
+#define GCC_SDCC4_BCR						11
+#define GCC_TSIF_BCR						12
+#define GCC_UFS_CARD_BCR					13
+#define GCC_UFS_PHY_BCR						14
+#define GCC_USB30_PRIM_BCR					15
+#define GCC_USB30_SEC_BCR					16
+#define GCC_USB3_PHY_PRIM_BCR					17
+#define GCC_USB3PHY_PHY_PRIM_BCR				18
+#define GCC_USB3_DP_PHY_PRIM_BCR				19
+#define GCC_USB3_PHY_SEC_BCR					20
+#define GCC_USB3PHY_PHY_SEC_BCR					21
+#define GCC_USB3_DP_PHY_SEC_BCR					22
+#define GCC_USB_PHY_CFG_AHB2PHY_BCR				23
+#define GCC_PCIE_0_PHY_BCR					24
+#define GCC_PCIE_1_PHY_BCR					25
+
+/* GCC GDSCRs */
+#define PCIE_0_GDSC						0
+#define PCIE_1_GDSC						1
+#define UFS_CARD_GDSC						2
+#define UFS_PHY_GDSC						3
+#define USB30_PRIM_GDSC						4
+#define USB30_SEC_GDSC						5
+#define HLOS1_VOTE_AGGRE_NOC_MMU_AUDIO_TBU_GDSC			6
+#define HLOS1_VOTE_AGGRE_NOC_MMU_PCIE_TBU_GDSC			7
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU1_GDSC			8
+#define HLOS1_VOTE_AGGRE_NOC_MMU_TBU2_GDSC			9
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC			10
+#define HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC			11
+#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC			12
+
+#endif
diff --git a/tools/k3_gen_x509_cert.sh b/tools/k3_gen_x509_cert.sh
index 298cec13137..24cfc4e5fb5 100755
--- a/tools/k3_gen_x509_cert.sh
+++ b/tools/k3_gen_x509_cert.sh
@@ -13,6 +13,7 @@ LOADADDR=0x41c00000
 BOOTCORE_OPTS=0
 BOOTCORE=16
 DEBUG_TYPE=0
+SWRV=1
 
 gen_degen_template() {
 cat << 'EOF' > degen-template.txt
@@ -70,7 +71,7 @@ cat << 'EOF' > x509-template.txt
  shaValue = FORMAT:HEX,OCT:TEST_IMAGE_SHA_VAL
 
  [ swrv ]
- swrv = INTEGER:0
+ swrv = INTEGER:TEST_SWRV
 
 # [ encryption ]
 # initalVector = FORMAT:HEX,OCT:TEST_IMAGE_ENC_IV
@@ -153,8 +154,9 @@ options_help[o]="output_file:Name of the final output file. default to $OUTPUT"
 options_help[c]="core_id:target core id on which the image would be running. Default to $BOOTCORE"
 options_help[l]="loadaddr: Target load address of the binary in hex. Default to $LOADADDR"
 options_help[d]="debug_type: Debug type, set to 4 to enable early JTAG. Default to $DEBUG_TYPE"
+options_help[r]="SWRV: Software Rev for X509 certificate"
 
-while getopts "b:k:o:c:l:d:h" opt
+while getopts "b:k:o:c:l:d:h:r:" opt
 do
 	case $opt in
 	b)
@@ -175,6 +177,9 @@ do
 	d)
 		DEBUG_TYPE=$OPTARG
 	;;
+        r)
+		SWRV=$OPTARG
+	;;
 	h)
 		usage
 		exit 0
@@ -230,6 +235,7 @@ gen_cert() {
 	#echo "	IMAGE_SIZE = $BIN_SIZE"
 	#echo "	CERT_TYPE = $CERTTYPE"
 	#echo "	DEBUG_TYPE = $DEBUG_TYPE"
+	echo " SWRV = $SWRV"
 	sed -e "s/TEST_IMAGE_LENGTH/$BIN_SIZE/"	\
 		-e "s/TEST_IMAGE_SHA_VAL/$SHA_VAL/" \
 		-e "s/TEST_CERT_TYPE/$CERTTYPE/" \
@@ -237,6 +243,7 @@ gen_cert() {
 		-e "s/TEST_BOOT_CORE/$BOOTCORE/" \
 		-e "s/TEST_BOOT_ADDR/$ADDR/" \
 		-e "s/TEST_DEBUG_TYPE/$DEBUG_TYPE/" \
+                -e "s/TEST_SWRV/$SWRV/" \
 		x509-template.txt > $TEMP_X509
 	openssl req -new -x509 -key $KEY -nodes -outform DER -out $CERT -config $TEMP_X509 -sha512
 }