diff options
| author | Jonas Karlman <jonas@kwiboo.se> | 2023-07-22 13:30:16 +0000 |
|---|---|---|
| committer | Kever Yang <kever.yang@rock-chips.com> | 2023-07-28 18:45:03 +0800 |
| commit | bed7b2f00b1346f712f849d53c72fa8642601115 (patch) | |
| tree | 0afd8b9e96b9a497397689f3906921f27c4d2048 | |
| parent | 5e030632d49367944879e17a6d73828be22edd55 (diff) | |
pci: pcie_dw_rockchip: Get config region from reg prop
Get the config region to use from the reg prop. Also update the
referenced region index used in comment.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| -rw-r--r-- | drivers/pci/pcie_dw_common.c | 10 | ||||
| -rw-r--r-- | drivers/pci/pcie_dw_rockchip.c | 7 |
2 files changed, 13 insertions, 4 deletions
diff --git a/drivers/pci/pcie_dw_common.c b/drivers/pci/pcie_dw_common.c index 9f8b016d114..74fb6df412c 100644 --- a/drivers/pci/pcie_dw_common.c +++ b/drivers/pci/pcie_dw_common.c @@ -141,9 +141,9 @@ static uintptr_t set_cfg_address(struct pcie_dw *pcie, /* * Not accessing root port configuration space? - * Region #0 is used for Outbound CFG space access. + * Region #1 is used for Outbound CFG space access. * Direction = Outbound - * Region Index = 0 + * Region Index = 1 */ d = PCI_MASK_BUS(d); d = PCI_ADD_BUS(bus, d); @@ -328,8 +328,10 @@ void pcie_dw_setup_host(struct pcie_dw *pci) pci->prefetch.bus_start = hose->regions[ret].bus_start; /* PREFETCH_bus_addr */ pci->prefetch.size = hose->regions[ret].size; /* PREFETCH size */ } else if (hose->regions[ret].flags == PCI_REGION_SYS_MEMORY) { - pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size); - pci->cfg_size = pci->io.size; + if (!pci->cfg_base) { + pci->cfg_base = (void *)(pci->io.phys_start - pci->io.size); + pci->cfg_size = pci->io.size; + } } else { dev_err(pci->dev, "invalid flags type!\n"); } diff --git a/drivers/pci/pcie_dw_rockchip.c b/drivers/pci/pcie_dw_rockchip.c index 6da618055cb..83737e62bc6 100644 --- a/drivers/pci/pcie_dw_rockchip.c +++ b/drivers/pci/pcie_dw_rockchip.c @@ -366,6 +366,13 @@ static int rockchip_pcie_parse_dt(struct udevice *dev) dev_dbg(dev, "APB address is 0x%p\n", priv->apb_base); + priv->dw.cfg_base = dev_read_addr_size_index_ptr(dev, 2, + &priv->dw.cfg_size); + if (!priv->dw.cfg_base) + return -EINVAL; + + dev_dbg(dev, "CFG address is 0x%p\n", priv->dw.cfg_base); + ret = gpio_request_by_name(dev, "reset-gpios", 0, &priv->rst_gpio, GPIOD_IS_OUT); if (ret) { |