diff options
| author | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-12-26 14:17:34 +0800 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2023-12-27 17:29:07 +0800 |
| commit | bf12bb99d870cccb666011c917cf3510f9b2d9a2 (patch) | |
| tree | f5c28be2862bc79f63a6ae6c78cd688a9e093c32 | |
| parent | b0469041c09e80fdef56a6c8938f8fc74a385a24 (diff) | |
andes: cpu: Enable memboost feature
Andes CPU has memboost feature including prefetch,
write-around and non-blocking load. Enable them by default.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/andesv5/cpu.c | 9 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-andes/csr.h | 6 |
2 files changed, 14 insertions, 1 deletions
diff --git a/arch/riscv/cpu/andesv5/cpu.c b/arch/riscv/cpu/andesv5/cpu.c index e764f6c5c07..a23b7948d92 100644 --- a/arch/riscv/cpu/andesv5/cpu.c +++ b/arch/riscv/cpu/andesv5/cpu.c @@ -31,8 +31,11 @@ void harts_early_init(void) /* Enable I/D-cache in SPL */ if (CONFIG_IS_ENABLED(RISCV_MMODE)) { unsigned long mcache_ctl_val = csr_read(CSR_MCACHE_CTL); + unsigned long mmisc_ctl_val = csr_read(CSR_MMISC_CTL); - mcache_ctl_val |= MCACHE_CTL_CCTL_SUEN; + mcache_ctl_val |= (MCACHE_CTL_CCTL_SUEN | \ + MCACHE_CTL_IC_PREFETCH_EN | MCACHE_CTL_DC_PREFETCH_EN | \ + MCACHE_CTL_DC_WAROUND_EN | MCACHE_CTL_L2C_WAROUND_EN); if (!CONFIG_IS_ENABLED(SYS_ICACHE_OFF)) mcache_ctl_val |= MCACHE_CTL_IC_EN; @@ -52,5 +55,9 @@ void harts_early_init(void) while (!(csr_read(CSR_MCACHE_CTL) & MCACHE_CTL_DC_COHSTA)); } } + + mmisc_ctl_val |= MMISC_CTL_NON_BLOCKING_EN; + + csr_write(CSR_MMISC_CTL, mmisc_ctl_val); } } diff --git a/arch/riscv/include/asm/arch-andes/csr.h b/arch/riscv/include/asm/arch-andes/csr.h index 12d5eb6f6c2..3f3f05b348a 100644 --- a/arch/riscv/include/asm/arch-andes/csr.h +++ b/arch/riscv/include/asm/arch-andes/csr.h @@ -19,9 +19,15 @@ #define MCACHE_CTL_IC_EN BIT(0) #define MCACHE_CTL_DC_EN BIT(1) #define MCACHE_CTL_CCTL_SUEN BIT(8) +#define MCACHE_CTL_IC_PREFETCH_EN BIT(9) +#define MCACHE_CTL_DC_PREFETCH_EN BIT(10) +#define MCACHE_CTL_DC_WAROUND_EN BIT(13) +#define MCACHE_CTL_L2C_WAROUND_EN BIT(15) #define MCACHE_CTL_DC_COHEN BIT(19) #define MCACHE_CTL_DC_COHSTA BIT(20) +/* mmisc_ctl register */ +#define MMISC_CTL_NON_BLOCKING_EN BIT(8) #define CCTL_L1D_WBINVAL_ALL 6 |