diff options
| author | Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com> | 2025-07-02 12:27:17 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-07-08 15:01:25 +0200 |
| commit | bfa3f147e1b5df74db8cdffbef5a276d2c2daec3 (patch) | |
| tree | 0b5e51277aa180e897af6570c7cf3af231bb6417 | |
| parent | 92fcd3c16839d0bd51b743596017cbd0d1b2e9b6 (diff) | |
spi: cadence_qspi: Set tshsl_ns to at least one sclk_ns
tshsl_ns is the clock delay for chip select deassert. This is the delay in
master reference clocks for the length that the master mode chip select
outputs are de-asserted between transactions.
The minimum delay is always SCLK period to ensure the chip select is never
re-asserted within one SCLK period.
That is why tshsl_ns delay should be at least one sclk_ns value. If it is
less than sclk_ns, set it equal to sclk_ns.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@amd.com>
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250702065717.3871435-1-venkatesh.abbarapu@amd.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 76569a8019b..ebfcae9a5b3 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -303,6 +303,10 @@ void cadence_qspi_apb_delay(void *reg_base, tshsl_ns -= sclk_ns + ref_clk_ns; if (tchsh_ns >= sclk_ns + 3 * ref_clk_ns) tchsh_ns -= sclk_ns + 3 * ref_clk_ns; + + if (tshsl_ns < sclk_ns) + tshsl_ns = sclk_ns; + tshsl = DIV_ROUND_UP(tshsl_ns, ref_clk_ns); tchsh = DIV_ROUND_UP(tchsh_ns, ref_clk_ns); tslch = DIV_ROUND_UP(tslch_ns, ref_clk_ns); |