diff options
| author | Ye Li <ye.li@nxp.com> | 2021-10-29 09:46:16 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-02-05 13:38:38 +0100 |
| commit | d563d29203de33e2d35b6c39e0e0c7f38cb51f3d (patch) | |
| tree | 369b8f68083898a56bf8b91e4aff8f9c69e595d0 | |
| parent | 961ac7873520d661d3ad2bf4c6390f21bcad536a (diff) | |
arm: imx8ulp: Allocate LPAV resources to AP domain
When single boot, assign AP domain as the master domain of the LPAV.
Allocates LPAV master and slave resources like GPU, DCNano, MIPI-DSI
eDMA channel and eDMA request to APD
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/soc.c | 22 |
1 files changed, 16 insertions, 6 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index b25f5f2521d..7898cb0ed92 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -466,6 +466,20 @@ static int trdc_set_access(void) return 0; } +void lpav_configure(void) +{ + /* LPAV to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x44, BIT(7)); + + /* GPU 2D/3D/DCNANO/MIPI_DSI to APD */ + setbits_le32(SIM_SEC_BASE_ADDR + 0x4c, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + + /* LPAV slave/dma2 ch allocation and request allocation to APD */ + writel(0x1f, SIM_SEC_BASE_ADDR + 0x50); + writel(0xffffffff, SIM_SEC_BASE_ADDR + 0x54); + writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); +} + int arch_cpu_init(void) { if (IS_ENABLED(CONFIG_SPL_BUILD)) { @@ -486,12 +500,8 @@ int arch_cpu_init(void) release_rdc(RDC_TRDC); trdc_set_access(); - /* LPAV to APD */ - setbits_le32(0x2802B044, BIT(7)); - /* GPU 2D/3D to APD */ - setbits_le32(0x2802B04C, BIT(1) | BIT(2)); - /* DCNANO and MIPI_DSI to APD */ - setbits_le32(0x2802B04C, BIT(1) | BIT(2) | BIT(3) | BIT(4)); + + lpav_configure(); } /* Release xrdc, then allow A35 to write SRAM2 */ |