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authorNeha Malcom Francis <n-francis@ti.com>2023-09-27 18:39:55 +0530
committerTom Rini <trini@konsulko.com>2023-10-04 14:16:01 -0400
commitd73851be435d4ed205b3f72a6e0a405c679d8bc1 (patch)
tree46968cf4ee86ea256227b61edbeccce86dc6a33b
parent5b2671594b80af116e259313d48bcd580d71f462 (diff)
arm: dts: k3-j721e-r5: Clean up inclusion hierarchy
Get rid of k3-j721e-r5-*-u-boot.dtsi as it is not necessary. Change the inclusion hierarchy to be as follows: k3-j721e-<board>.dts--- - -->k3-j721e-r5-<board>.dts - k3-j721e-<board>-u-boot.dtsi--- Reason for explicitly mentioning the inclusion of -u-boot.dtsi in code although it could've been automatically done by U-Boot is to resolve some of the dependencies that R5 file requires. Also remove duplicate phandles while making this shift as well as remove firmware-loader as it serves no purpose without "phandlepart" property. Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
-rw-r--r--arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi29
-rw-r--r--arch/arm/dts/k3-j721e-r5-common-proc-board.dts38
-rw-r--r--arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi31
-rw-r--r--arch/arm/dts/k3-j721e-r5-sk.dts47
4 files changed, 16 insertions, 129 deletions
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
deleted file mode 100644
index f9746d33ec9..00000000000
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board-u-boot.dtsi
+++ /dev/null
@@ -1,29 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
- */
-
-#include "k3-j721e-common-proc-board-u-boot.dtsi"
-
-/ {
- chosen {
- firmware-loader = &fs_loader0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- };
-
- fs_loader0: fs_loader@0 {
- bootph-all;
- compatible = "u-boot,fs-loader";
- };
-};
-
-&tps659413a {
- esm: esm {
- compatible = "ti,tps659413-esm";
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
index 32f71e9b6ac..7bb5ce775c2 100644
--- a/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
+++ b/arch/arm/dts/k3-j721e-r5-common-proc-board.dts
@@ -5,10 +5,10 @@
/dts-v1/;
-#include "k3-j721e-som-p0.dtsi"
+#include "k3-j721e-common-proc-board.dts"
#include "k3-j721e-ddr-evm-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
-#include "k3-j721e-binman.dtsi"
+#include "k3-j721e-common-proc-board-u-boot.dtsi"
#include <dt-bindings/phy/phy-cadence.h>
/ {
@@ -198,27 +198,6 @@
>;
};
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
- >;
- };
-
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- J721E_IOPAD(0x25c, PIN_INPUT, 0) /* (R28) MMC1_SDWP */
- >;
- };
-
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
@@ -300,6 +279,11 @@
bootph-pre-ram;
};
};
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
};
};
@@ -424,14 +408,6 @@
assigned-clocks = <&serdes0 CDNS_SIERRA_PLL_CMNLC>, <&serdes0 CDNS_SIERRA_PLL_CMNLC1>;
assigned-clock-parents = <&wiz0_pll1_refclk>, <&wiz0_pll1_refclk>;
- serdes0_pcie_link: link@0 {
- reg = <0>;
- cdns,num-lanes = <1>;
- #phy-cells = <0>;
- cdns,phy-type = <PHY_TYPE_PCIE>;
- resets = <&serdes_wiz0 1>;
- };
-
serdes0_qsgmii_link: phy@1 {
reg = <1>;
cdns,num-lanes = <1>;
diff --git a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi b/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
deleted file mode 100644
index 733d69cd008..00000000000
--- a/arch/arm/dts/k3-j721e-r5-sk-u-boot.dtsi
+++ /dev/null
@@ -1,31 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * Copyright (C) 2021 Texas Instruments Incorporated - https://www.ti.com/
- */
-
-#include "k3-j721e-sk-u-boot.dtsi"
-
-/ {
- chosen {
- firmware-loader = &fs_loader0;
- };
-
- aliases {
- remoteproc0 = &sysctrler;
- remoteproc1 = &a72_0;
- remoteproc2 = &main_r5fss0_core0;
- remoteproc3 = &main_r5fss0_core1;
- };
-
- fs_loader0: fs_loader@0 {
- bootph-all;
- compatible = "u-boot,fs-loader";
- };
-};
-
-&tps659412 {
- esm: esm {
- compatible = "ti,tps659413-esm";
- bootph-pre-ram;
- };
-};
diff --git a/arch/arm/dts/k3-j721e-r5-sk.dts b/arch/arm/dts/k3-j721e-r5-sk.dts
index 6986292e37c..1cc64d07f75 100644
--- a/arch/arm/dts/k3-j721e-r5-sk.dts
+++ b/arch/arm/dts/k3-j721e-r5-sk.dts
@@ -5,9 +5,10 @@
/dts-v1/;
-#include "k3-j721e.dtsi"
+#include "k3-j721e-sk.dts"
#include "k3-j721e-ddr-sk-lp4-4266.dtsi"
#include "k3-j721e-ddr.dtsi"
+#include "k3-j721e-sk-u-boot.dtsi"
/ {
model = "Texas Instruments J721E SK R5";
@@ -15,6 +16,8 @@
aliases {
remoteproc0 = &sysctrler;
remoteproc1 = &a72_0;
+ remoteproc2 = &main_r5fss0_core0;
+ remoteproc3 = &main_r5fss0_core1;
};
chosen {
@@ -279,52 +282,15 @@
J721E_WKUP_IOPAD(0x8, PIN_INPUT, 0) /* (D21) MCU_OSPI0_DQS */
>;
};
-
- mcu_i2c0_pins_default: mcu_i2c0_pins_default {
- pinctrl-single,pins = <
- J721E_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (J26) MCU_I2C0_SCL */
- J721E_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (H25) MCU_I2C0_SDA */
- >;
- };
};
&main_pmx0 {
- main_uart0_pins_default: main_uart0_pins_default {
- bootph-pre-ram;
- pinctrl-single,pins = <
- J721E_IOPAD(0x1f0, PIN_INPUT, 0) /* (AC2) UART0_CTSn */
- J721E_IOPAD(0x1f4, PIN_OUTPUT, 0) /* (AB1) UART0_RTSn */
- J721E_IOPAD(0x1e8, PIN_INPUT, 0) /* (AB2) UART0_RXD */
- J721E_IOPAD(0x1ec, PIN_OUTPUT, 0) /* (AB3) UART0_TXD */
- >;
- };
-
- main_usbss0_pins_default: main_usbss0_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x290, PIN_OUTPUT, 0) /* (U6) USB0_DRVVBUS */
- J721E_IOPAD(0x210, PIN_INPUT, 7) /* (W3) MCAN1_RX.GPIO1_3 */
- >;
- };
-
main_usbss1_pins_default: main-usbss1-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x214, PIN_OUTPUT, 4) /* (V4) MCAN1_TX.USB1_DRVVBUS */
>;
};
- main_mmc1_pins_default: main_mmc1_pins_default {
- pinctrl-single,pins = <
- J721E_IOPAD(0x254, PIN_INPUT, 0) /* (R29) MMC1_CMD */
- J721E_IOPAD(0x250, PIN_INPUT, 0) /* (P25) MMC1_CLK */
- J721E_IOPAD(0x2ac, PIN_INPUT, 0) /* (P25) MMC1_CLKLB */
- J721E_IOPAD(0x24c, PIN_INPUT, 0) /* (R24) MMC1_DAT0 */
- J721E_IOPAD(0x248, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */
- J721E_IOPAD(0x244, PIN_INPUT, 0) /* (R25) MMC1_DAT2 */
- J721E_IOPAD(0x240, PIN_INPUT, 0) /* (R26) MMC1_DAT3 */
- J721E_IOPAD(0x258, PIN_INPUT, 0) /* (P23) MMC1_SDCD */
- >;
- };
-
main_i2c0_pins_default: main-i2c0-pins-default {
pinctrl-single,pins = <
J721E_IOPAD(0x220, PIN_INPUT_PULLUP, 0) /* (AC5) I2C0_SCL */
@@ -423,6 +389,11 @@
bootph-pre-ram;
};
};
+
+ esm: esm {
+ compatible = "ti,tps659413-esm";
+ bootph-pre-ram;
+ };
};
};