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| author | Michal Simek <michal.simek@amd.com> | 2024-11-01 10:49:53 +0100 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2024-11-06 19:42:48 +0800 |
| commit | d86ff34285fed658715b36639e3336f03038cc1c (patch) | |
| tree | 30fcd49ecd85c765c22771b3bbfe20b6a9b0fbe0 | |
| parent | e83a99cb674ecc5cda222ad44f4bd270c5f9561f (diff) | |
xilinx: mbv: Place DTB by default to DDR location
DTB should be also placed to DDR. It should be the part of commit
9d688e6da5c9 ("riscv: mbv: Align DT with QEMU").
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | board/xilinx/Kconfig | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig index c7df4ab5781..0ff8440e6e0 100644 --- a/board/xilinx/Kconfig +++ b/board/xilinx/Kconfig @@ -45,7 +45,7 @@ config XILINX_OF_BOARD_DTB_ADDR default 0x1000 if ARCH_VERSAL || ARCH_VERSAL_NET || ARCH_VERSAL2 default 0x8000 if MICROBLAZE default 0x100000 if ARCH_ZYNQ || ARCH_ZYNQMP - default 0x23000000 if TARGET_XILINX_MBV + default 0x83000000 if TARGET_XILINX_MBV depends on OF_BOARD || OF_SEPARATE help Offset in the memory where the board configuration DTB is placed. |