diff options
| author | Marek Vasut <marex@denx.de> | 2021-09-14 05:25:32 +0200 |
|---|---|---|
| committer | Ramon Fried <rfried.dev@gmail.com> | 2021-09-28 18:50:55 +0300 |
| commit | dc5d07179211432365f9f367799c0b72eb754160 (patch) | |
| tree | 43a39fbb005250ee4d21695444beb47d6f009453 | |
| parent | 563b90cc946842fb30298ef59f150f9c642fa4a1 (diff) | |
arm: socfpga: vining: Set default SPI NOR mode and frequency
The SPI NOR bus mode is 0 on this system, update it accordingly.
Increase frequency to 40 MHz and enable SFDP parsing, since the
flashes on this system support that and it is a huge performance
improvement.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
| -rw-r--r-- | configs/socfpga_vining_fpga_defconfig | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 5d8970e57ca..4dcf4f7bf9e 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -74,6 +74,9 @@ CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=70 CONFIG_MMC_DW=y CONFIG_MTD=y +CONFIG_SF_DEFAULT_MODE=0x0 +CONFIG_SF_DEFAULT_SPEED=40000000 +CONFIG_SPI_FLASH_SFDP_SUPPORT=y CONFIG_SPI_FLASH_SPANSION=y CONFIG_SPI_FLASH_STMICRO=y # CONFIG_SPI_FLASH_USE_4K_SECTORS is not set |