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authorMichal Simek <michal.simek@xilinx.com>2022-05-11 11:52:50 +0200
committerMichal Simek <michal.simek@amd.com>2022-05-18 13:17:54 +0200
commitdda356db648ba3ee6f52efe790b0fa925868258b (patch)
tree423c2d068fda8b1873e3d500e74058269108cdfe
parent07f8e78af0637204e5ae33067d6ca17d34b181f6 (diff)
arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM
There are couple of IPs which are enabled in origin HW design which are missing in SOM dt. Add them to match default setup. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Link: https://lore.kernel.org/r/901401beacbea5931fc18cde20c157e5978a7023.1652262769.git.michal.simek@amd.com
-rw-r--r--arch/arm/dts/zynqmp-sm-k26-revA.dts95
1 files changed, 95 insertions, 0 deletions
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts
index 8b2cd512da5..35fab915172 100644
--- a/arch/arm/dts/zynqmp-sm-k26-revA.dts
+++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts
@@ -356,3 +356,98 @@
&zynqmp_dpsub {
status = "okay";
};
+
+&rtc {
+ status = "okay";
+};
+
+&lpd_dma_chan1 {
+ status = "okay";
+};
+
+&lpd_dma_chan2 {
+ status = "okay";
+};
+
+&lpd_dma_chan3 {
+ status = "okay";
+};
+
+&lpd_dma_chan4 {
+ status = "okay";
+};
+
+&lpd_dma_chan5 {
+ status = "okay";
+};
+
+&lpd_dma_chan6 {
+ status = "okay";
+};
+
+&lpd_dma_chan7 {
+ status = "okay";
+};
+
+&lpd_dma_chan8 {
+ status = "okay";
+};
+
+&fpd_dma_chan1 {
+ status = "okay";
+};
+
+&fpd_dma_chan2 {
+ status = "okay";
+};
+
+&fpd_dma_chan3 {
+ status = "okay";
+};
+
+&fpd_dma_chan4 {
+ status = "okay";
+};
+
+&fpd_dma_chan5 {
+ status = "okay";
+};
+
+&fpd_dma_chan6 {
+ status = "okay";
+};
+
+&fpd_dma_chan7 {
+ status = "okay";
+};
+
+&fpd_dma_chan8 {
+ status = "okay";
+};
+
+&gpu {
+ status = "okay";
+};
+
+&lpd_watchdog {
+ status = "okay";
+};
+
+&watchdog0 {
+ status = "okay";
+};
+
+&cpu_opp_table {
+ opp00 {
+ opp-hz = /bits/ 64 <1333333333>;
+ };
+ opp01 {
+ opp-hz = /bits/ 64 <666666666>;
+ };
+ opp02 {
+ opp-hz = /bits/ 64 <444444444>;
+ };
+ opp03 {
+ opp-hz = /bits/ 64 <333333333>;
+ };
+};