diff options
| author | Masahisa Kojima <masahisa.kojima@linaro.org> | 2022-05-17 17:41:38 +0900 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-06-10 13:37:32 -0400 |
| commit | de9f2c9c2ed8ee4ffadc3909a46c17888fed619f (patch) | |
| tree | 93cd820b2762f1cc82b1f85c9c3374b4fc3b7e8e | |
| parent | 88d50ed8a15fc4a0df37e2a274607827a52a2217 (diff) | |
spi: synquacer: DMSTART bit must not be set while transferring
DMSTART bit must not be set while there is active transfer.
This commit sets the DMSTART bit only when the transfer begins.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Signed-off-by: Satoru Okamoto <okamoto.satoru@socionext.com>
Acked-by: Jassi Brar <jaswinder.singh@linaro.org>
| -rw-r--r-- | drivers/spi/spi-synquacer.c | 8 |
1 files changed, 5 insertions, 3 deletions
diff --git a/drivers/spi/spi-synquacer.c b/drivers/spi/spi-synquacer.c index f1422cf893e..5e1b3aedc73 100644 --- a/drivers/spi/spi-synquacer.c +++ b/drivers/spi/spi-synquacer.c @@ -330,9 +330,11 @@ static int synquacer_spi_xfer(struct udevice *dev, unsigned int bitlen, writel(~0, priv->base + RXC); /* Trigger */ - val = readl(priv->base + DMSTART); - val |= BIT(TRIGGER); - writel(val, priv->base + DMSTART); + if (flags & SPI_XFER_BEGIN) { + val = readl(priv->base + DMSTART); + val |= BIT(TRIGGER); + writel(val, priv->base + DMSTART); + } while (busy & (BIT(RXBIT) | BIT(TXBIT))) { if (priv->rx_words) |