diff options
| author | Prasanth Babu Mantena <p-mantena@ti.com> | 2025-07-16 12:34:07 +0530 |
|---|---|---|
| committer | Michal Simek <michal.simek@amd.com> | 2025-07-24 09:04:04 +0200 |
| commit | e6345dfc2a5c86e66cac3372152e3295cfaf1ee2 (patch) | |
| tree | 0f91e840c119c69a0cf78a8fdaa7c70326a7f413 | |
| parent | ee56866f11c9a64b15470ba7165399068818d269 (diff) | |
Revert "spi: cadence_qspi: Fix odd byte write issue in STIG mode"
The buffer that is being used to write into the flash needs
to be handled properly with padding of 0xFF. The place that
this is done can be at a more generic place like spi-nor core.
This reverts commit cd9123507003e07b13e61d72e14e493bb338e827.
Signed-off-by: Prasanth Babu Mantena <p-mantena@ti.com>
Reviewed-by: Neha Malcom Francis <n-francis@ti.com>
Reviewed-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Link: https://lore.kernel.org/r/20250716070407.2082524-1-p-mantena@ti.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
| -rw-r--r-- | drivers/spi/cadence_qspi_apb.c | 3 |
1 files changed, 0 insertions, 3 deletions
diff --git a/drivers/spi/cadence_qspi_apb.c b/drivers/spi/cadence_qspi_apb.c index 6f89d3add5d..4696c09f754 100644 --- a/drivers/spi/cadence_qspi_apb.c +++ b/drivers/spi/cadence_qspi_apb.c @@ -559,9 +559,6 @@ int cadence_qspi_apb_command_write(struct cadence_spi_priv *priv, u8 opcode; if (priv->dtr) - txlen += txlen & 1; - - if (priv->dtr) opcode = op->cmd.opcode >> 8; else opcode = op->cmd.opcode; |