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| author | Michal Simek <michal.simek@xilinx.com> | 2020-10-05 15:43:44 +0200 |
|---|---|---|
| committer | Michal Simek <michal.simek@xilinx.com> | 2020-10-27 08:13:31 +0100 |
| commit | e9284066958e906118b3fd71d7e81e9916b2c58a (patch) | |
| tree | 9e3d5223fc098f91a3c5563f06e7887ca11844d8 | |
| parent | 0d76b71d93f6d7740b973dbb50010dc8f7b347f0 (diff) | |
arm64: zynqmp: Enable FPGA loading from SPL
fpga bitstream needs to be listed in config node in FIT image. Only tested
option is bitstream in BIN format.
Enabling this feature increase code size by almost 4k.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| -rw-r--r-- | configs/xilinx_zynqmp_virt_defconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/configs/xilinx_zynqmp_virt_defconfig b/configs/xilinx_zynqmp_virt_defconfig index 264b662ece1..5b4fe537c31 100644 --- a/configs/xilinx_zynqmp_virt_defconfig +++ b/configs/xilinx_zynqmp_virt_defconfig @@ -19,6 +19,7 @@ CONFIG_USE_PREBOOT=y # CONFIG_DISPLAY_CPUINFO is not set CONFIG_BOARD_EARLY_INIT_F=y CONFIG_BOARD_EARLY_INIT_R=y +CONFIG_SPL_FPGA=y CONFIG_SPL_OS_BOOT=y CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_RAM_DEVICE=y |