diff options
| author | Yao Zi <ziyao@disroot.org> | 2025-06-06 04:28:02 +0000 |
|---|---|---|
| committer | Leo Yu-Chi Liang <ycliang@andestech.com> | 2025-07-03 16:14:13 +0800 |
| commit | f28911368eaf1b403e85ac0346fadee3fa21b6c4 (patch) | |
| tree | 398277b032d84a0f609a84aba1d5f1427cb29371 | |
| parent | 5afad3d4a314464af34f9c312d3028b9053f1135 (diff) | |
riscv: cpu: th1520: Add a routine to bring up secondary cores
On coldboot, only HART 0 among the four HARTs of TH1520 is brought up by
hardware, and the remaining HARTs are in reset states, requiring manual
setup of reset address and deassertion to function normal. Introduce a
routine to do the work.
Signed-off-by: Yao Zi <ziyao@disroot.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
| -rw-r--r-- | arch/riscv/cpu/th1520/cpu.c | 29 | ||||
| -rw-r--r-- | arch/riscv/include/asm/arch-th1520/cpu.h | 1 |
2 files changed, 29 insertions, 1 deletions
diff --git a/arch/riscv/cpu/th1520/cpu.c b/arch/riscv/cpu/th1520/cpu.c index b83f1272c67..f60446fd772 100644 --- a/arch/riscv/cpu/th1520/cpu.c +++ b/arch/riscv/cpu/th1520/cpu.c @@ -9,8 +9,35 @@ #include <asm/io.h> #include <cpu_func.h> +#include <linux/bitops.h> -#define TH1520_PMP_BASE (void *)0xffdc020000 +#define TH1520_C910_RST (void __iomem *)(0xffef014000 + 0x004) +#define TH1520_C910_CORE_RST_N(n) BIT((n) + 1) +#define TH1520_SYSCFG_AP_BASE (void __iomem *)(0xffef018000) +#define TH1520_SYSCFG_CORE_START_L(n) (TH1520_SYSCFG_AP_BASE + 0x50 + 8 * (n)) +#define TH1520_SYSCFG_CORE_START_H(n) (TH1520_SYSCFG_AP_BASE + 0x54 + 8 * (n)) +#define TH1520_PMP_BASE (void *)0xffdc020000 + +void th1520_kick_secondary_cores(void) +{ + int i; + + /* + * On coldboot, only HART 0 is brought up by hardware, and resets for + * secondary cores are asserted. Set reset address of secondary cores + * to the entry of SPL, then deassert the resets to bring them up. + */ + for (i = 1; i < 4; i++) { + writel(CONFIG_SPL_TEXT_BASE & 0xffffffff, + TH1520_SYSCFG_CORE_START_L(i)); + writel(CONFIG_SPL_TEXT_BASE >> 32, + TH1520_SYSCFG_CORE_START_H(i)); + } + + setbits_le32(TH1520_C910_RST, TH1520_C910_CORE_RST_N(1) | + TH1520_C910_CORE_RST_N(2) | + TH1520_C910_CORE_RST_N(3)); +} void th1520_invalidate_pmp(void) { diff --git a/arch/riscv/include/asm/arch-th1520/cpu.h b/arch/riscv/include/asm/arch-th1520/cpu.h index 837f0b8d06b..e164e9ab979 100644 --- a/arch/riscv/include/asm/arch-th1520/cpu.h +++ b/arch/riscv/include/asm/arch-th1520/cpu.h @@ -5,5 +5,6 @@ #ifndef _ASM_TH1520_CPU_H_ #define _ASM_TH1520_CPU_H_ +void th1520_kick_secondary_cores(void); void th1520_invalidate_pmp(void); #endif /* _ASM_TH1520_CPU_H_ */ |