diff options
| author | Marek Vasut <marex@denx.de> | 2024-10-15 22:14:53 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-10-18 14:18:33 -0600 |
| commit | f83e36fd83c74b4e28a45a9d56abc4ad9b7848b9 (patch) | |
| tree | 62b844f6784dad65b58afb7f1b345a82d61e7271 | |
| parent | 7f453771528160f0401a8cb7cd871c32e56f63f2 (diff) | |
mtd: spi-nor: Move SR3 WPS bit definition in the correct location
Move the SR3 bit definition in the right place. Fix
what is likely a rebase artifact. No functional change.
Fixes: 215f1d5794c6 ("mtd: spi-nor: Clear Winbond SR3 WPS bit on boot")
Signed-off-by: Marek Vasut <marex@denx.de>
| -rw-r--r-- | include/linux/mtd/spi-nor.h | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/include/linux/mtd/spi-nor.h b/include/linux/mtd/spi-nor.h index 1ae586b2e5f..655a6d197ea 100644 --- a/include/linux/mtd/spi-nor.h +++ b/include/linux/mtd/spi-nor.h @@ -182,15 +182,15 @@ /* Status Register 2 bits. */ #define SR2_QUAD_EN_BIT7 BIT(7) +/* Status Register 3 bits. */ +#define SR3_WPS BIT(2) + /* * Maximum number of flashes that can be connected * in stacked/parallel configuration */ #define SNOR_FLASH_CNT_MAX 2 -/* Status Register 3 bits. */ -#define SR3_WPS BIT(2) - /* For Cypress flash. */ #define SPINOR_OP_RD_ANY_REG 0x65 /* Read any register */ #define SPINOR_OP_WR_ANY_REG 0x71 /* Write any register */ |