diff options
| author | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2024-10-11 17:31:49 +0200 |
|---|---|---|
| committer | Patrick Delaunay <patrick.delaunay@foss.st.com> | 2024-10-16 20:18:56 +0200 |
| commit | f9e94edab49188ee9aefe6979825defff20b151e (patch) | |
| tree | 9a509fa5f162584f28b9f94d5c4004d342d8e0ef | |
| parent | 5cb33c70b2c57248eb552e57fba8af305fa3b2c8 (diff) | |
ARM: stm32mp: enable data cache after LMB configuration for STM32MP1
Move the stm32mp1 data cache reconfiguration after the lmb init call
board_r::initr_lmb to allow parsing of the reserved region with
no-map tag.
After this patch the DDR is not fully mapped up to arch_early_init_r()
call, only the relocation region is mapped, but it is enough for
the first board_r initialization phases; later, when arch_early_init_r()
is called, the LMB is already initialized and the function
lmb_is_reserved_flags() function is functional, this LMB function
is called in the weak function dram_bank_mmu_setup() when
dcache_enable() is executed.
Without this change, as LMB is not initialized when it is used in
dram_bank_mmu_setup, the OP-TEE region is mapped cache-able by U-Boot
and we have some firewall violation since "LMB memory map global and
persistent" series.
Fixes: ed17a33fed29 ("lmb: make LMB memory map persistent and global")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| -rw-r--r-- | arch/arm/mach-stm32mp/Kconfig | 2 | ||||
| -rw-r--r-- | arch/arm/mach-stm32mp/stm32mp1/cpu.c | 7 |
2 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index d5934a92771..25663a99464 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -39,6 +39,7 @@ choice config STM32MP13X bool "Support STMicroelectronics STM32MP13x Soc" + select ARCH_EARLY_INIT_R select ARM_SMCCC select CPU_V7A select CPU_V7_HAS_NONSEC @@ -57,6 +58,7 @@ config STM32MP13X config STM32MP15X bool "Support STMicroelectronics STM32MP15x Soc" + select ARCH_EARLY_INIT_R select ARCH_SUPPORT_PSCI select BINMAN select CPU_V7A diff --git a/arch/arm/mach-stm32mp/stm32mp1/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c index 26c073f06a0..62cc98910a7 100644 --- a/arch/arm/mach-stm32mp/stm32mp1/cpu.c +++ b/arch/arm/mach-stm32mp/stm32mp1/cpu.c @@ -143,6 +143,11 @@ void enable_caches(void) { /* I-cache is already enabled in start.S: icache_enable() not needed */ + /* keep D-cache configuration done before relocation, wait arch_early_init_r*/ +} + +int arch_early_init_r(void) +{ /* deactivate the data cache, early enabled in arch_cpu_init() */ dcache_disable(); /* @@ -150,6 +155,8 @@ void enable_caches(void) * warning: the TLB location udpated in board_f.c::reserve_mmu */ dcache_enable(); + + return 0; } static void setup_boot_mode(void) |