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| author | Suman Anna <s-anna@ti.com> | 2020-08-17 18:15:10 -0500 |
|---|---|---|
| committer | Lokesh Vutla <lokeshvutla@ti.com> | 2020-09-15 18:51:53 +0530 |
| commit | 10c4de02f0f0e424d196a47fb933f2d619966cfe (patch) | |
| tree | 0183af7f4ee1d43dd227897858cfdd42abb16eec /api/api_platform-mips.c | |
| parent | 7873e9df8fc47fb2532112e7fe4ad546f7a46fcb (diff) | |
arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Diffstat (limited to 'api/api_platform-mips.c')
0 files changed, 0 insertions, 0 deletions