Merge tag 'arc-updates-for-2018.07-rc1' of git://git.denx.de/u-boot-arc

Here we do a couple of minor fixes like:
 - Move .ivt section to the very beginning of the image
   by default which allows us to use that image put right
   at reset vector (usually 0x0)

 - Improve relocation fix-up which became required once
   we moved .ivt and understood a problem with existing implementation
   where we relied on a particular placement of sections.
   Now we don't care about placement because we just explicitly
   check for .text and in case of ARCompact .ivt sections

 - Re-implemnt do_reset() such that it calls reset_cpu() which
   could implmented for a particular board

And hte most important part we introduce support for yet another
devboard from Synopsys - EMDK.

1 files changed, 8 insertions, 4 deletions

diff --git a/arch/arc/lib/cache.c b/arch/arc/lib/cache.c
index 6f52877643c..8c1cb6e8009 100644
--- a/arch/arc/lib/cache.c
+++ b/arch/arc/lib/cache.c
@@ -432,9 +432,16 @@ void read_decode_cache_bcr(void)
 	int dc_line_sz = 0, ic_line_sz = 0;
 	union bcr_di_cache ibcr, dbcr;
 
+	/*
+	 * We don't care much about I$ line length really as there're
+	 * no per-line ops on I$ instead we only do full invalidation of it
+	 * on occasion of relocation and right before jumping to the OS.
+	 * Still we check insane config with zero-encoded line length in
+	 * presense of version field in I$ BCR. Just in case.
+	 */
 	ibcr.word = read_aux_reg(ARC_BCR_IC_BUILD);
 	if (ibcr.fields.ver) {
-		gd->arch.l1_line_sz = ic_line_sz = 8 << ibcr.fields.line_len;
+		ic_line_sz = 8 << ibcr.fields.line_len;
 		if (!ic_line_sz)
 			panic("Instruction exists but line length is 0\n");
 	}
@@ -445,9 +452,6 @@ void read_decode_cache_bcr(void)
 		if (!dc_line_sz)
 			panic("Data cache exists but line length is 0\n");
 	}
-
-	if (ic_line_sz && dc_line_sz && (ic_line_sz != dc_line_sz))
-		panic("Instruction and data cache line lengths differ\n");
 }
 
 void cache_init(void)