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| author | Tom Rini <trini@konsulko.com> | 2018-01-19 16:07:36 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2018-01-19 16:07:36 -0500 |
| commit | c4cb6e64bf068eaa1f7c96cb37da7ae6d40bbbff (patch) | |
| tree | d386f09db756c2ecd869ae9dfcbee02e89aa327e /arch/arc/lib/start.S | |
| parent | e8b9fdced641bbc6edb0a2c85f6000edaedf8b2e (diff) | |
| parent | 8f44e1ee799d75eb2b296a7525dc0c3003a3644c (diff) | |
Merge git://git.denx.de/u-boot-arc
Diffstat (limited to 'arch/arc/lib/start.S')
| -rw-r--r-- | arch/arc/lib/start.S | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/arc/lib/start.S b/arch/arc/lib/start.S index 95d64f9d437..0d72fe71d42 100644 --- a/arch/arc/lib/start.S +++ b/arch/arc/lib/start.S @@ -44,6 +44,14 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_IC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_IC_IVIC] + ; As per ARC HS databook (see chapter 5.3.3.2) + ; it is required to add 3 NOPs after each write to IC_IVIC. + nop + nop + nop + 1: ; Disable/enable D-cache according to configuration lr r5, [ARC_BCR_DC_BUILD] @@ -57,6 +65,10 @@ ENTRY(_start) #endif sr r5, [ARC_AUX_DC_CTRL] + mov r5, 1 + sr r5, [ARC_AUX_DC_IVDC] + + 1: #ifdef CONFIG_ISA_ARCV2 ; Disable System-Level Cache (SLC) |