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| author | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-21 20:13:48 +0200 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2014-04-21 20:13:48 +0200 |
| commit | 94b972d366c29b92319865e3ded16da062aa8507 (patch) | |
| tree | 2948fd62cdd789f182775f5d7d576ac9b7b025e5 /arch/arm/cpu/arm720t/tegra114/cpu.c | |
| parent | dda0dbfc69f3d560c87f5be85f127ed862ea6721 (diff) | |
| parent | d381294aef4a5b6ddeda3685519330a5b73d884f (diff) | |
Merge branch 'u-boot-tegra/master' into 'u-boot-arm/master'
Diffstat (limited to 'arch/arm/cpu/arm720t/tegra114/cpu.c')
| -rw-r--r-- | arch/arm/cpu/arm720t/tegra114/cpu.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/arm/cpu/arm720t/tegra114/cpu.c b/arch/arm/cpu/arm720t/tegra114/cpu.c index d10b96a1d45..5ed3bb9d9ab 100644 --- a/arch/arm/cpu/arm720t/tegra114/cpu.c +++ b/arch/arm/cpu/arm720t/tegra114/cpu.c @@ -34,8 +34,8 @@ static void enable_cpu_power_rail(void) debug("enable_cpu_power_rail entry\n"); /* un-tristate PWR_I2C SCL/SDA, rest of the defaults are correct */ - pinmux_tristate_disable(PINGRP_PWR_I2C_SCL); - pinmux_tristate_disable(PINGRP_PWR_I2C_SDA); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SCL_PZ6); + pinmux_tristate_disable(PMUX_PINGRP_PWR_I2C_SDA_PZ7); /* * Set CPUPWRGOOD_TIMER - APB clock is 1/2 of SCLK (102MHz), |