diff options
| author | Sean Anderson <sean.anderson@seco.com> | 2022-03-22 16:59:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2022-04-01 16:56:53 -0400 |
| commit | e75d791c5083cd7d25c36677825b2a01ce708b7d (patch) | |
| tree | fbf94028bacc54b09768df62fa0fb1fca6544801 /arch/arm/cpu/armv8/exceptions.S | |
| parent | e97ac4780d69c719b81086bba615c8568afd14a1 (diff) | |
arm64: Save spsr in pt_regs
This register holds "pstate" which includes (among other things) the
instruction mode the CPU was in when the exception was taken. This is
necessary to correctly interpret instructions at elr.
Signed-off-by: Sean Anderson <sean.anderson@seco.com>
Diffstat (limited to 'arch/arm/cpu/armv8/exceptions.S')
| -rw-r--r-- | arch/arm/cpu/armv8/exceptions.S | 5 |
1 files changed, 4 insertions, 1 deletions
diff --git a/arch/arm/cpu/armv8/exceptions.S b/arch/arm/cpu/armv8/exceptions.S index 001913f429a..504d566721c 100644 --- a/arch/arm/cpu/armv8/exceptions.S +++ b/arch/arm/cpu/armv8/exceptions.S @@ -77,15 +77,18 @@ _save_el_regs: switch_el x11, 3f, 2f, 1f 3: mrs x1, esr_el3 mrs x2, elr_el3 + mrs x3, spsr_el3 b 0f 2: mrs x1, esr_el2 mrs x2, elr_el2 + mrs x3, spsr_el2 b 0f 1: mrs x1, esr_el1 mrs x2, elr_el1 + mrs x3, spsr_el1 0: stp x1, x0, [sp, #-16]! - stp xzr, x2, [sp, #-16]! + stp x3, x2, [sp, #-16]! mov x0, sp ret |