diff options
| author | Tom Rini <trini@konsulko.com> | 2020-07-17 08:04:28 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-07-17 08:04:28 -0400 |
| commit | 42e7659db0ac7089d3a2f80ee1c3b8eb64d84706 (patch) | |
| tree | c2b2dda157f71ce80ca4fb00332519f161896a5c /arch/arm/include/asm/arch-imx8m/ddr.h | |
| parent | fee68b98fe3890631a9bdf8f8db328179011ee3f (diff) | |
| parent | ab8b4e818cbc3846672c13b12f1d75daccfac519 (diff) | |
Merge tag 'u-boot-imx-20200716' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
i.MX for 2020.10
----------------
- i.MX DDR driver fix/update for i.MX8M
- i.MX pinctrl driver fix.
- Use arm_smccc_smc to remove imx sip function
- i.MX8M clk update
- support booting aarch32 kernel on aarch64 hardware
- fused part support for i.MX8MP
- imx6: pcm058 to DM
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/708734785
Diffstat (limited to 'arch/arm/include/asm/arch-imx8m/ddr.h')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/ddr.h | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 7a2a2d8edce..0f1e832c038 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -529,6 +529,8 @@ enum msg_response { #define DDRC_SBRWDATA0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf2c) #define DDRC_SBRWDATA1(X) (DDRC_IPS_BASE_ADDR(X) + 0xf30) #define DDRC_PDCH(X) (DDRC_IPS_BASE_ADDR(X) + 0xf34) +#define DDRC_SBRSTART0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf38) +#define DDRC_SBRRANGE0(X) (DDRC_IPS_BASE_ADDR(X) + 0xf40) #define DDRC_FREQ1_DERATEEN(X) (DDRC_IPS_BASE_ADDR(X) + 0x2020) #define DDRC_FREQ1_DERATEINT(X) (DDRC_IPS_BASE_ADDR(X) + 0x2024) @@ -708,12 +710,20 @@ int ddr_cfg_phy(struct dram_timing_info *timing_info); void load_lpddr4_phy_pie(void); void ddrphy_trained_csr_save(struct dram_cfg_param *param, unsigned int num); void dram_config_save(struct dram_timing_info *info, unsigned long base); +void board_dram_ecc_scrub(void); +void ddrc_inline_ecc_scrub(unsigned int start_address, + unsigned int range_address); +void ddrc_inline_ecc_scrub_end(unsigned int start_address, + unsigned int range_address); /* utils function for ddr phy training */ int wait_ddrphy_training_complete(void); void ddrphy_init_set_dfi_clk(unsigned int drate); void ddrphy_init_read_msg_block(enum fw_type type); +void update_umctl2_rank_space_setting(unsigned int pstat_num); +void get_trained_CDD(unsigned int fsp); + static inline void reg32_write(unsigned long addr, u32 val) { writel(val, addr); |