diff options
| author | Ye Li <ye.li@nxp.com> | 2022-07-26 16:41:07 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-07-26 11:29:01 +0200 |
| commit | 99c7cc58e12d59a7562c637b7c1510cfdf33e4f9 (patch) | |
| tree | 6f37204d0e08437af51e400e862d87fc53ccc1ae /arch/arm/include/asm/arch-imx8m/ddr.h | |
| parent | e631185a20ab730603d7bb04378e98a83d337735 (diff) | |
ddr: imx: Add i.MX9 DDR controller driver
Since i.MX9 uses same DDR PHY with i.MX8M, split the DDRPHY to a common
directory under imx, then use dedicated ddr controller driver for each
iMX9 and iMX8M.
The DDRPHY registers are space compressed, so it needs conversion to
access the DDRPHY address. Introduce a common PHY address remap function
for both iMX8M and iMX9 for all PHY registers accessing.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/include/asm/arch-imx8m/ddr.h')
| -rw-r--r-- | arch/arm/include/asm/arch-imx8m/ddr.h | 6 |
1 files changed, 4 insertions, 2 deletions
diff --git a/arch/arm/include/asm/arch-imx8m/ddr.h b/arch/arm/include/asm/arch-imx8m/ddr.h index 2ce8a8f2d41..2f76e7d69b9 100644 --- a/arch/arm/include/asm/arch-imx8m/ddr.h +++ b/arch/arm/include/asm/arch-imx8m/ddr.h @@ -725,6 +725,8 @@ void update_umctl2_rank_space_setting(unsigned int pstat_num); void get_trained_CDD(unsigned int fsp); unsigned int lpddr4_mr_read(unsigned int mr_rank, unsigned int mr_addr); +ulong ddrphy_addr_remap(uint32_t paddr_apb_from_ctlr); + static inline void reg32_write(unsigned long addr, u32 val) { writel(val, addr); @@ -741,9 +743,9 @@ static inline void reg32setbit(unsigned long addr, u32 bit) } #define dwc_ddrphy_apb_wr(addr, data) \ - reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr), data) + reg32_write(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr), data) #define dwc_ddrphy_apb_rd(addr) \ - reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + 4 * (addr)) + reg32_read(IP2APB_DDRPHY_IPS_BASE_ADDR(0) + ddrphy_addr_remap(addr)) extern struct dram_cfg_param ddrphy_trained_csr[]; extern uint32_t ddrphy_trained_csr_num; |