ARM: imx: ddr: Add deskew register programming

Fill is code for programming the DDR_PHY_CMD_DESKEW_CONx registers,
which are optional, but can be used to fill in the byte lane delays.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: NXP i.MX U-Boot Team <uboot-imx@nxp.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>

1 files changed, 13 insertions, 3 deletions

diff --git a/arch/arm/include/asm/arch-mx7/mx7-ddr.h b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
index bea5dd8ec5e..8ac721114cc 100644
--- a/arch/arm/include/asm/arch-mx7/mx7-ddr.h
+++ b/arch/arm/include/asm/arch-mx7/mx7-ddr.h
@@ -136,11 +136,21 @@ struct ddr_phy {
 	u32 offset_wr_con0;	/* 0x0030 */
 	u32 reserved5[0x07];
 	u32 cmd_sdll_con0;	/* 0x0050 */
-	u32 reserved6[0x12];
+	u32 reserved6[0x06];
+	u32 cmd_lvl_con0;	/* 0x006c */
+	u32 reserved7[0x02];
+	u32 cmd_lvl_con3;	/* 0x0078 */
+	u32 cmd_deskew_con0;	/* 0x007c */
+	u32 cmd_deskew_con1;	/* 0x0080 */
+	u32 cmd_deskew_con2;	/* 0x0084 */
+	u32 cmd_deskew_con3;	/* 0x0088 */
+	u32 reserved8[0x02];
+	u32 cmd_deskew_con4;	/* 0x0094 */
+	u32 reserved9;
 	u32 drvds_con0;		/* 0x009c */
-	u32 reserved7[0x04];
+	u32 reserved10[0x04];
 	u32 mdll_con0;		/* 0x00b0 */
-	u32 reserved8[0x03];
+	u32 reserved11[0x03];
 	u32 zq_con0;		/* 0x00c0 */
 };