diff options
| author | Vikas Manocha <vikas.manocha@st.com> | 2016-02-11 15:47:20 -0800 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2016-02-24 18:43:57 -0500 |
| commit | e66c49fa930ed002c507ae0217b4b274c25675fb (patch) | |
| tree | b9da51f6a376e8e3fa2fc556bc6d2b8cc45be29d /arch/arm/include/asm/arch-stm32f7/stm32.h | |
| parent | 6a12cebd90a752b0214a65b152703ca63a941478 (diff) | |
stm32: add support for stm32f7 & stm32f746 discovery board
This patch adds support for stm32f7 family & stm32f746 board.
Signed-off-by: Vikas Manocha <vikas.manocha@st.com>
Diffstat (limited to 'arch/arm/include/asm/arch-stm32f7/stm32.h')
| -rw-r--r-- | arch/arm/include/asm/arch-stm32f7/stm32.h | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-stm32f7/stm32.h b/arch/arm/include/asm/arch-stm32f7/stm32.h new file mode 100644 index 00000000000..713eb2e8cf7 --- /dev/null +++ b/arch/arm/include/asm/arch-stm32f7/stm32.h @@ -0,0 +1,63 @@ +/* + * (C) Copyright 2016 + * Vikas Manocha, STMicroelectronics, <vikas.manocha@st.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _ASM_ARCH_HARDWARE_H +#define _ASM_ARCH_HARDWARE_H + +/* STM32F746 */ +#define ITCM_FLASH_BASE 0x00200000UL +#define AXIM_FLASH_BASE 0x08000000UL + +#define ITCM_SRAM_BASE 0x00000000UL +#define DTCM_SRAM_BASE 0x20000000UL +#define SRAM1_BASE 0x20010000UL +#define SRAM2_BASE 0x2004C000UL + +#define PERIPH_BASE 0x40000000UL + +#define APB1_PERIPH_BASE (PERIPH_BASE + 0x00000000) +#define APB2_PERIPH_BASE (PERIPH_BASE + 0x00010000) +#define AHB1_PERIPH_BASE (PERIPH_BASE + 0x00020000) +#define AHB2_PERIPH_BASE (PERIPH_BASE + 0x10000000) +#define AHB3_PERIPH_BASE (PERIPH_BASE + 0x20000000) + +#define TIM2_BASE (APB1_PERIPH_BASE + 0x0000) +#define USART2_BASE (APB1_PERIPH_BASE + 0x4400) +#define USART3_BASE (APB1_PERIPH_BASE + 0x4800) +#define PWR_BASE (APB1_PERIPH_BASE + 0x7000) + +#define USART1_BASE (APB2_PERIPH_BASE + 0x1000) +#define USART6_BASE (APB2_PERIPH_BASE + 0x1400) + +#define STM32_GPIOA_BASE (AHB1_PERIPH_BASE + 0x0000) +#define STM32_GPIOB_BASE (AHB1_PERIPH_BASE + 0x0400) +#define STM32_GPIOC_BASE (AHB1_PERIPH_BASE + 0x0800) +#define STM32_GPIOD_BASE (AHB1_PERIPH_BASE + 0x0C00) +#define STM32_GPIOE_BASE (AHB1_PERIPH_BASE + 0x1000) +#define STM32_GPIOF_BASE (AHB1_PERIPH_BASE + 0x1400) +#define STM32_GPIOG_BASE (AHB1_PERIPH_BASE + 0x1800) +#define STM32_GPIOH_BASE (AHB1_PERIPH_BASE + 0x1C00) +#define STM32_GPIOI_BASE (AHB1_PERIPH_BASE + 0x2000) +#define STM32_GPIOJ_BASE (AHB1_PERIPH_BASE + 0x2400) +#define STM32_GPIOK_BASE (AHB1_PERIPH_BASE + 0x2800) +#define RCC_BASE (AHB1_PERIPH_BASE + 0x3800) +#define FLASH_CNTL_BASE (AHB1_PERIPH_BASE + 0x3C00) + + +#define SDRAM_FMC_BASE (AHB3_PERIPH_BASE + 0x4A0000140) + +enum clock { + CLOCK_CORE, + CLOCK_AHB, + CLOCK_APB1, + CLOCK_APB2 +}; +#define STM32_BUS_MASK 0xFFFF0000 + +int configure_clocks(void); + +#endif /* _ASM_ARCH_HARDWARE_H */ |