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authorTom Rini <trini@konsulko.com>2017-08-04 07:23:32 -0400
committerTom Rini <trini@konsulko.com>2017-08-04 07:23:32 -0400
commitfe84c48eeb8e9cb0b8b80a4c0a53bb089adff9af (patch)
tree7b3d2b47abc9b9f11f0e79a591f590050912c68a /arch/arm/include/asm/arch-zynqmp/hardware.h
parent217324b23c4a73420633068efcdc396682894b1b (diff)
parentdf1cd46fb84922735e1c12f54b7202b0268dcddd (diff)
Merge tag 'xilinx-for-v2017.09' of git://www.denx.de/git/u-boot-microblaze
Xilinx changes for v2017.09 Zynq: - Add Z-Turn board support fpga: - Remove intermediate buffer from code Zynqmp: - dts cleanup - change psu_init handling - Add options to get silicon version - Fix time handling - Map OCM/TCM via MMU - Add new clock driver
Diffstat (limited to 'arch/arm/include/asm/arch-zynqmp/hardware.h')
-rw-r--r--arch/arm/include/asm/arch-zynqmp/hardware.h12
1 files changed, 3 insertions, 9 deletions
diff --git a/arch/arm/include/asm/arch-zynqmp/hardware.h b/arch/arm/include/asm/arch-zynqmp/hardware.h
index cf187f31110..cab29ba0369 100644
--- a/arch/arm/include/asm/arch-zynqmp/hardware.h
+++ b/arch/arm/include/asm/arch-zynqmp/hardware.h
@@ -48,18 +48,9 @@ struct crlapb_regs {
#define crlapb_base ((struct crlapb_regs *)ZYNQMP_CRL_APB_BASEADDR)
#define ZYNQMP_IOU_SCNTR_SECURE 0xFF260000
-#define ZYNQMP_IOU_SCNTR 0xFF250000
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_EN 0x1
#define ZYNQMP_IOU_SCNTR_COUNTER_CONTROL_REGISTER_HDBG 0x2
-struct iou_scntr {
- u32 counter_control_register;
- u32 reserved0[7];
- u32 base_frequency_id_register;
-};
-
-#define iou_scntr ((struct iou_scntr *)ZYNQMP_IOU_SCNTR)
-
struct iou_scntr_secure {
u32 counter_control_register;
u32 reserved0[7];
@@ -153,4 +144,7 @@ struct pmu_regs {
#define pmu_base ((struct pmu_regs *)ZYNQMP_PMU_BASEADDR)
+#define ZYNQMP_CSU_IDCODE_ADDR 0xFFCA0040
+#define ZYNQMP_CSU_VER_ADDR 0xFFCA0044
+
#endif /* _ASM_ARCH_HARDWARE_H */