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authorTom Rini <trini@konsulko.com>2015-05-05 07:00:11 -0400
committerTom Rini <trini@konsulko.com>2015-05-05 07:00:11 -0400
commit3f2f1a00394eb7ce7176f9d0930e40e55ba2c79c (patch)
treec91bddf10c0a179153e674309779e0afd4ab72ae /arch/arm/include/asm/armv7.h
parent622da1c36aee9c39075f2109848228a5737925c0 (diff)
parentb939689c7b87773c44275a578ffc8674a867e39d (diff)
Merge branch 'master' of git://git.denx.de/u-boot-arm
Diffstat (limited to 'arch/arm/include/asm/armv7.h')
-rw-r--r--arch/arm/include/asm/armv7.h10
1 files changed, 10 insertions, 0 deletions
diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h
index 58d8b161215..cbe7dc1a5c6 100644
--- a/arch/arm/include/asm/armv7.h
+++ b/arch/arm/include/asm/armv7.h
@@ -70,6 +70,16 @@
#define CP15DSB asm volatile ("mcr p15, 0, %0, c7, c10, 4" : : "r" (0))
#define CP15DMB asm volatile ("mcr p15, 0, %0, c7, c10, 5" : : "r" (0))
+#ifdef __ARM_ARCH_7A__
+#define ISB asm volatile ("isb" : : : "memory")
+#define DSB asm volatile ("dsb" : : : "memory")
+#define DMB asm volatile ("dmb" : : : "memory")
+#else
+#define ISB CP15ISB
+#define DSB CP15DSB
+#define DMB CP15DMB
+#endif
+
/*
* Workaround for ARM errata # 798870
* Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been