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authorTom Rini <trini@konsulko.com>2021-03-03 14:05:43 -0500
committerTom Rini <trini@konsulko.com>2021-03-03 14:05:43 -0500
commit5a9d8633e5e5f5253010480fb0db3742b0ea1356 (patch)
tree6cef337796d50552504a3f0b90e07d32d2d88190 /arch/arm/include/asm/system.h
parentc5219c4a18f2b27547ecd799914f94e48b0fa86f (diff)
parent63af92e837f3d7c21ab5fc4a96ffcbf202efaf90 (diff)
Merge branch '2021-03-03-assorted-improvements' into next
- Clean up reset_cpu() - Assorted arm cp15 cleanups - Assorted cleanups throughout the tree from Simon - TPM1 / TPM2 cleanups
Diffstat (limited to 'arch/arm/include/asm/system.h')
-rw-r--r--arch/arm/include/asm/system.h18
1 files changed, 2 insertions, 16 deletions
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h
index 5fe83699f43..11fceec4d2f 100644
--- a/arch/arm/include/asm/system.h
+++ b/arch/arm/include/asm/system.h
@@ -397,20 +397,6 @@ static inline void set_cr(unsigned int val)
isb();
}
-static inline unsigned int get_dacr(void)
-{
- unsigned int val;
- asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc");
- return val;
-}
-
-static inline void set_dacr(unsigned int val)
-{
- asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR"
- : : "r" (val) : "cc");
- isb();
-}
-
#ifdef CONFIG_ARMV7_LPAE
/* Long-Descriptor Translation Table Level 1/2 Bits */
#define TTB_SECT_XN_MASK (1ULL << 54)
@@ -475,7 +461,7 @@ enum dcache_option {
#define TTB_SECT_XN_MASK (1 << 4)
#define TTB_SECT_C_MASK (1 << 3)
#define TTB_SECT_B_MASK (1 << 2)
-#define TTB_SECT (2 << 0)
+#define TTB_SECT (2 << 0)
/*
* Short-descriptor format memory region attributes, without TEX remap
@@ -489,7 +475,7 @@ enum dcache_option {
*/
enum dcache_option {
DCACHE_OFF = TTB_SECT_DOMAIN(0) | TTB_SECT_XN_MASK | TTB_SECT,
- DCACHE_WRITETHROUGH = DCACHE_OFF | TTB_SECT_C_MASK,
+ DCACHE_WRITETHROUGH = TTB_SECT_DOMAIN(0) | TTB_SECT | TTB_SECT_C_MASK,
DCACHE_WRITEBACK = DCACHE_WRITETHROUGH | TTB_SECT_B_MASK,
DCACHE_WRITEALLOC = DCACHE_WRITEBACK | TTB_SECT_TEX(1),
};