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authorTom Rini <trini@konsulko.com>2021-03-03 14:05:43 -0500
committerTom Rini <trini@konsulko.com>2021-03-03 14:05:43 -0500
commit5a9d8633e5e5f5253010480fb0db3742b0ea1356 (patch)
tree6cef337796d50552504a3f0b90e07d32d2d88190 /arch/arm/lib/cache-cp15.c
parentc5219c4a18f2b27547ecd799914f94e48b0fa86f (diff)
parent63af92e837f3d7c21ab5fc4a96ffcbf202efaf90 (diff)
Merge branch '2021-03-03-assorted-improvements' into next
- Clean up reset_cpu() - Assorted arm cp15 cleanups - Assorted cleanups throughout the tree from Simon - TPM1 / TPM2 cleanups
Diffstat (limited to 'arch/arm/lib/cache-cp15.c')
-rw-r--r--arch/arm/lib/cache-cp15.c13
1 files changed, 5 insertions, 8 deletions
diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c
index 24050e5bdd3..aab1bf43607 100644
--- a/arch/arm/lib/cache-cp15.c
+++ b/arch/arm/lib/cache-cp15.c
@@ -22,10 +22,6 @@ __weak void arm_init_before_mmu(void)
{
}
-__weak void arm_init_domains(void)
-{
-}
-
static void set_section_phys(int section, phys_addr_t phys,
enum dcache_option option)
{
@@ -203,11 +199,12 @@ static inline void mmu_setup(void)
asm volatile("mcr p15, 0, %0, c2, c0, 0"
: : "r" (gd->arch.tlb_addr) : "memory");
#endif
- /* Set the access control to all-supervisor */
+ /*
+ * initial value of Domain Access Control Register (DACR)
+ * Set the access control to client (1U) for each of the 16 domains
+ */
asm volatile("mcr p15, 0, %0, c3, c0, 0"
- : : "r" (~0));
-
- arm_init_domains();
+ : : "r" (0x55555555));
/* and enable the mmu */
reg = get_cr(); /* get control reg. */