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authorPatrick Delaunay <patrick.delaunay@foss.st.com>2021-02-05 13:53:33 +0100
committerTom Rini <trini@konsulko.com>2021-03-02 15:53:37 -0500
commitaad84147945f27fffeccb84053399ff11447c9d6 (patch)
tree2234ca1282c026b0908a2b445273358b0e0e2468 /arch/arm/lib/cache-cp15.c
parent1419e5b5167e6ff35882473b81741d0815c453ea (diff)
stm32mp: update the mmu configuration for SPL and prereloc
Overidde the weak function dram_bank_mmu_setup() to set the DDR (preloc case) or the SYSRAM (in SPL case) executable before to enable the MMU and configure DACR. This weak function is called in dcache_enable/mmu_setup. This patchs avoids a permission access issue when the DDR is marked executable (by calling mmu_set_region_dcache_behaviour with DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission activation with DACR in dcache_enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Diffstat (limited to 'arch/arm/lib/cache-cp15.c')
0 files changed, 0 insertions, 0 deletions