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authorTom Rini <trini@konsulko.com>2023-04-03 16:45:41 -0400
committerTom Rini <trini@konsulko.com>2023-04-03 16:45:41 -0400
commit288fe30a2367b8d0e3f416493150a38ebaa88459 (patch)
tree1f841eb95d9ceeda4aa3255fb1132a0342f9b19a /arch/arm/lib/cache.c
parentfd4ed6b7e83ec3aea9a2ce21baea8ca9676f40dd (diff)
parent9876c8c147144db2c120fcc9ffa6de27f6894441 (diff)
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/lib/cache.c')
-rw-r--r--arch/arm/lib/cache.c9
1 files changed, 9 insertions, 0 deletions
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c
index 1a589c7e2a0..7a160158671 100644
--- a/arch/arm/lib/cache.c
+++ b/arch/arm/lib/cache.c
@@ -159,6 +159,15 @@ __weak int arm_reserve_mmu(void)
*/
gd->arch.tlb_allocated = gd->arch.tlb_addr;
#endif
+
+ if (IS_ENABLED(CONFIG_CMO_BY_VA_ONLY)) {
+ /*
+ * As invalidate_dcache_all() will be called before
+ * mmu_setup(), we should make sure that the PTs are
+ * already in a valid state.
+ */
+ memset((void *)gd->arch.tlb_addr, 0, gd->arch.tlb_size);
+ }
#endif
return 0;