diff options
| author | Jerome Forissier <jerome.forissier@linaro.org> | 2025-04-04 15:50:35 +0200 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2025-04-14 08:59:39 -0600 |
| commit | 6fe50e39508043f386fc1bd40bbc02b8a75c1940 (patch) | |
| tree | 0aac1d9565fef925db1e0610a5399ee33a747f76 /arch/arm/lib/cache.c | |
| parent | d08653d3699c1aafada3418c9f74b887bfb21a65 (diff) | |
arm: asm/system.h: mrc and mcr need .arm if __thumb2__ is not set
The mcr and msr instructions are available in Thumb mode only if
Thumb2 is supported. Therefore, if __thumb2__ is not set, make
sure we switch to ARM mode by inserting a .arm directive in the
inline assembly.
Fixes LTO link errors with kirkwood platforms, triggered by a later
commit:
tools/buildman/buildman -o /tmp/build -eP sheevaplug
[...]
{standard input}:24085: Error: selected processor does not support `mrc p15,0,r3,c1,c0,0' in Thumb mode
Signed-off-by: Jerome Forissier <jerome.forissier@linaro.org>
Diffstat (limited to 'arch/arm/lib/cache.c')
| -rw-r--r-- | arch/arm/lib/cache.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index dd19bd3e4fb..ed6f15cb570 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -10,6 +10,7 @@ #include <malloc.h> #include <asm/cache.h> #include <asm/global_data.h> +#include <asm/system.h> #include <linux/errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -126,8 +127,8 @@ void invalidate_l2_cache(void) { unsigned int val = 0; - asm volatile("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" - : : "r" (val) : "cc"); + asm_arm_or_thumb2("mcr p15, 1, %0, c15, c11, 0 @ invl l2 cache" + : : "r" (val) : "cc"); isb(); } #endif |