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| author | Tom Rini <trini@konsulko.com> | 2023-08-18 13:45:58 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-08-18 13:45:58 -0400 |
| commit | 3881c9fbb7fdd98f6eae5cd33f7e9abe9455a585 (patch) | |
| tree | 3522dea6d6e5bff9c2d9bcae8354e16223c5b518 /arch/arm/lib | |
| parent | 14ba0a8bbc342a677982acc787ae542b84ed7993 (diff) | |
| parent | 48f792e31b88343bfccbaf73808e3d02a2be90dc (diff) | |
Merge branch '2023-08-18-assorted-updates' into next
- Use built-in ffs/fls on ARM, fix a PIE issue in SPL on ARMv8, bcm283x
and mediatek updates, whitespace fix in UFS uclass, make CI use
"tools-only" defconfig for more tests, add TI TCA9554 GPIO support,
cache alignment fix for SCSI, and fix a problem with
SYS_MMCSD_RAW_MODE_ARGS_SECTOR in SPL.
Diffstat (limited to 'arch/arm/lib')
| -rw-r--r-- | arch/arm/lib/Makefile | 5 | ||||
| -rw-r--r-- | arch/arm/lib/bitops.S | 45 |
2 files changed, 50 insertions, 0 deletions
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index 62cf80f3739..b1bcd374662 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -113,6 +113,11 @@ AFLAGS_REMOVE_memset.o := -mthumb -mthumb-interwork AFLAGS_REMOVE_memcpy.o := -mthumb -mthumb-interwork AFLAGS_memset.o := -DMEMSET_NO_THUMB_BUILD AFLAGS_memcpy.o := -DMEMCPY_NO_THUMB_BUILD + +# This is only necessary to force ARM mode on THUMB1 targets. +ifneq ($(CONFIG_SYS_ARM_ARCH),4) +obj-y += bitops.o +endif endif endif diff --git a/arch/arm/lib/bitops.S b/arch/arm/lib/bitops.S new file mode 100644 index 00000000000..29d15246346 --- /dev/null +++ b/arch/arm/lib/bitops.S @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2023 Sean Anderson <sean.anderson@seco.com> + * + * ARM bitops to call when using THUMB1, which doesn't have these instructions. + */ +#include <linux/linkage.h> +#include <asm/assembler.h> + +.pushsection .text.__fls +ENTRY(__fls) + clz r0, r0 + rsb r0, r0, #31 + ret lr +ENDPROC(__fls) +.popsection + +.pushsection .text.__ffs +ENTRY(__ffs) + rsb r3, r0, #0 + and r0, r0, r3 + clz r0, r0 + rsb r0, r0, #31 + ret lr +ENDPROC(__ffs) +.popsection + +.pushsection .text.fls +ENTRY(fls) + cmp r0, #0 + clzne r0, r0 + rsbne r0, r0, #32 + ret lr +ENDPROC(fls) +.popsection + +.pushsection .text.ffs +ENTRY(ffs) + rsb r3, r0, #0 + and r0, r0, r3 + clz r0, r0 + rsb r0, r0, #32 + ret lr +ENDPROC(ffs) +.popsection |