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| author | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2023-01-09 11:30:08 -0500 |
| commit | cebdfc22da6eb81793b616e855bc4d6d89c1c7a6 (patch) | |
| tree | 44eaafcbe4866712d361304882e7d56ca0ef1682 /arch/arm/mach-exynos/dmc_init_ddr3.c | |
| parent | 62e2ad1ceafbfdf2c44d3dc1b6efc81e768a96b9 (diff) | |
| parent | fe33066d246462551f385f204690a11018336ac8 (diff) | |
Merge branch 'next'
Signed-off-by: Tom Rini <trini@konsulko.com>
Diffstat (limited to 'arch/arm/mach-exynos/dmc_init_ddr3.c')
| -rw-r--r-- | arch/arm/mach-exynos/dmc_init_ddr3.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/arm/mach-exynos/dmc_init_ddr3.c b/arch/arm/mach-exynos/dmc_init_ddr3.c index fa867f27f30..cad8ccc5315 100644 --- a/arch/arm/mach-exynos/dmc_init_ddr3.c +++ b/arch/arm/mach-exynos/dmc_init_ddr3.c @@ -236,7 +236,7 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int reset) * better have similar timings, since there's only a single adjustment that is * shared by both chips). */ -const unsigned int test_addr = CONFIG_SYS_SDRAM_BASE; +const unsigned int test_addr = CFG_SYS_SDRAM_BASE; /* Test pattern with which RAM will be tested */ static const unsigned int test_pattern[] = { |