diff options
| author | Ye Li <ye.li@nxp.com> | 2021-10-29 09:46:25 +0800 |
|---|---|---|
| committer | Stefano Babic <sbabic@denx.de> | 2022-02-05 13:38:39 +0100 |
| commit | 9c7fbebe5dd5d9daa9160b778432daef2a13f47f (patch) | |
| tree | edd9562a582ebb6ea3a1cd4491e4887edd208114 /arch/arm/mach-imx/imx8ulp/soc.c | |
| parent | 112b4cac9d9bd986a5c0e267193dff3e46bab68a (diff) | |
imx8ulp: Workaround LPOSC_TRIM fuse load issue
8ULP ROM should read the LPOSC trim BIAS fuse to fill the CGC0
LPOSCCTRL[7:0], but it writes a fixed value on A0.1 revision.
A0.2 will fix the issue in ROM. But A0.1 we have to workaround
it in SPL by setting LPOSCCTRL BIASCURRENT again.
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Diffstat (limited to 'arch/arm/mach-imx/imx8ulp/soc.c')
| -rw-r--r-- | arch/arm/mach-imx/imx8ulp/soc.c | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/arch/arm/mach-imx/imx8ulp/soc.c b/arch/arm/mach-imx/imx8ulp/soc.c index d9dca21e8c7..e12e28d9e7b 100644 --- a/arch/arm/mach-imx/imx8ulp/soc.c +++ b/arch/arm/mach-imx/imx8ulp/soc.c @@ -487,6 +487,26 @@ void lpav_configure(void) writel(0x003fffff, SIM_SEC_BASE_ADDR + 0x58); } +void load_lposc_fuse(void) +{ + int ret; + u32 val = 0, val2 = 0, reg; + + ret = fuse_read(25, 0, &val); + if (ret) + return; /* failed */ + + ret = fuse_read(25, 1, &val2); + if (ret) + return; /* failed */ + + /* LPOSCCTRL */ + reg = readl(0x2802f304); + reg &= ~0xff; + reg |= (val & 0xff); + writel(reg, 0x2802f304); +} + void set_lpav_qos(void) { /* Set read QoS of dcnano on LPAV NIC */ |