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| author | Tom Rini <trini@konsulko.com> | 2020-06-09 09:17:24 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-06-09 09:17:24 -0400 |
| commit | be79009f3b9bbdbce283e67a865121e576d790ea (patch) | |
| tree | e6f0288f2031c6e869c4e131f2692e47a43aa263 /arch/arm/mach-imx/mx7/ddr.c | |
| parent | e411a090cf7162626d54d72dfc4530986c788cdb (diff) | |
| parent | 385429680106f8612386e26564f69dccdd110620 (diff) | |
Merge tag 'u-boot-imx-20200609' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2020.07
-----------------
- mx53: mx53menlo Convert to DM_ETH, fix fail boot
- imx8mp_evk: fix boot issue
- MX6, display5: fix environment
- drop warnings (watchdog) for i.MX8mm i.mx8mp
- enable bootaux for i.MX8M
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/695929999
Diffstat (limited to 'arch/arm/mach-imx/mx7/ddr.c')
| -rw-r--r-- | arch/arm/mach-imx/mx7/ddr.c | 22 |
1 files changed, 19 insertions, 3 deletions
diff --git a/arch/arm/mach-imx/mx7/ddr.c b/arch/arm/mach-imx/mx7/ddr.c index 9713835bf27..d1e10a67887 100644 --- a/arch/arm/mach-imx/mx7/ddr.c +++ b/arch/arm/mach-imx/mx7/ddr.c @@ -13,6 +13,7 @@ #include <asm/arch/crm_regs.h> #include <asm/arch/mx7-ddr.h> #include <common.h> +#include <linux/delay.h> /* * Routine: mx7_dram_cfg @@ -37,8 +38,23 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; int i; - /* Assert DDR Controller preset and DDR PHY reset */ - writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK, &src_regs->ddrc_rcr); + /* + * iMX7D RM 9.2.4.9.3 Power removal flow Table 9-11. Re-enabling power + * row 2 says "Reset controller / PHY by driving core_ddrc_rst = 0 , + * aresetn_n = 0, presetn = 0. That means reset everything. + */ + writel(SRC_DDRC_RCR_DDRC_CORE_RST_MASK | SRC_DDRC_RCR_DDRC_PRST_MASK, + &src_regs->ddrc_rcr); + + /* + * iMX7D RM 6.2.7.26 SRC_DDRC_RCR says wait 30 cycles (of unknown). + * If we assume this is 30 cycles at 100 MHz (about the rate of a + * DRAM bus), that's 300 nS, so waiting 10 uS is more then plenty. + */ + udelay(10); + + /* De-assert DDR Controller 'preset' and DDR PHY reset */ + clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_PRST_MASK); /* DDR controller configuration */ writel(ddrc_regs_val->mstr, &ddrc_regs->mstr); @@ -71,7 +87,7 @@ void mx7_dram_cfg(struct ddrc *ddrc_regs_val, struct ddrc_mp *ddrc_mp_val, writel(ddrc_regs_val->odtcfg, &ddrc_regs->odtcfg); writel(ddrc_regs_val->odtmap, &ddrc_regs->odtmap); - /* De-assert DDR Controller preset and DDR PHY reset */ + /* De-assert DDR Controller 'core_ddrc_rstn' and 'aresetn' */ clrbits_le32(&src_regs->ddrc_rcr, SRC_DDRC_RCR_DDRC_CORE_RST_MASK); /* PHY configuration */ |