diff options
| author | Tom Rini <trini@konsulko.com> | 2020-05-25 14:09:42 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-05-25 14:09:42 -0400 |
| commit | 60c7facfc965af6ff8ea14ee26c9d49cd2d0ec22 (patch) | |
| tree | 7bc7f20aae283028bca5fde34205e3ab7fc618de /arch/arm/mach-k3/common.c | |
| parent | 71f70cfcf4a79a58682596e6b7769fe6f8f0c4d1 (diff) | |
| parent | c02712a7484918648e5dd09c092035c7eeb7794a (diff) | |
Merge tag 'ti-v2020.07-rc3' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti
- Enable DM_ETH on omap3_logic board
- Enable Caches in SPL for K3 platforms
- Enable backup boot mode support for J721E
- Update the DDR timings for AM654 EVM
- Add automated tests for RX-51
Diffstat (limited to 'arch/arm/mach-k3/common.c')
| -rw-r--r-- | arch/arm/mach-k3/common.c | 35 |
1 files changed, 35 insertions, 0 deletions
diff --git a/arch/arm/mach-k3/common.c b/arch/arm/mach-k3/common.c index 0cd34ac3c7e..9695b2236ec 100644 --- a/arch/arm/mach-k3/common.c +++ b/arch/arm/mach-k3/common.c @@ -410,3 +410,38 @@ void remove_fwl_configs(struct fwl_data *fwl_data, size_t fwl_data_size) } } } + +void spl_enable_dcache(void) +{ +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) + phys_addr_t ram_top = CONFIG_SYS_SDRAM_BASE; + + dram_init_banksize(); + + /* reserve TLB table */ + gd->arch.tlb_size = PGTABLE_SIZE; + + ram_top += get_effective_memsize(); + /* keep ram_top in the 32-bit address space */ + if (ram_top >= 0x100000000) + ram_top = (phys_addr_t) 0x100000000; + + gd->arch.tlb_addr = ram_top - gd->arch.tlb_size; + debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr, + gd->arch.tlb_addr + gd->arch.tlb_size); + + dcache_enable(); +#endif +} + +#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF)) +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +} + +void spl_board_prepare_for_boot_linux(void) +{ + dcache_disable(); +} +#endif |