arm: mach-omap2: load/start remoteproc IPU1/IPU2

First check the presence of the ipu firmware in the boot partition.
If present enable the ipu and the related clocks & then move
on to load the firmware and eventually start remoteproc IPU1/IPU2.

do_enable_clocks by default puts the clock domains into auto
which does not work well with reset. Hence adding do_enable_ipu_clocks
function.

Signed-off-by: Keerthy <j-keerthy@ti.com>
[Amjad: fix IPU1_LOAD_ADDR and compile warnings]
Signed-off-by: Amjad Ouled-Ameur <aouledameur@baylibre.com>

2 files changed, 94 insertions, 7 deletions

diff --git a/arch/arm/mach-omap2/omap5/hw_data.c b/arch/arm/mach-omap2/omap5/hw_data.c
index fa4e27063c5..e6bee48dfcb 100644
--- a/arch/arm/mach-omap2/omap5/hw_data.c
+++ b/arch/arm/mach-omap2/omap5/hw_data.c
@@ -377,6 +377,85 @@ struct vcores_data omap5430_volts_es2 = {
 };
 
 /*
+ * Enable IPU1 clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_ipu1_clocks(void)
+{
+	if (!IS_ENABLED(CONFIG_DRA7XX) ||
+	    !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+		return;
+
+	u32 const clk_domains[] = {
+		(*prcm)->cm_ipu_clkstctrl,
+		(*prcm)->cm_ipu1_clkstctrl,
+		0
+	};
+
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_ipu1_ipu1_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_l4per_gptimer11_clkctrl,
+		(*prcm)->cm1_abe_timer7_clkctrl,
+		(*prcm)->cm1_abe_timer8_clkctrl,
+		0
+	};
+	do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
+			     clk_modules_explicit_en_essential, 0);
+
+	/* Enable optional additional functional clock for IPU1 */
+	setbits_le32((*prcm)->cm_ipu1_ipu1_clkctrl,
+		     IPU1_CLKCTRL_CLKSEL_MASK);
+	/* Enable optional additional functional clock for IPU1 */
+	setbits_le32((*prcm)->cm1_abe_timer7_clkctrl,
+		     IPU1_CLKCTRL_CLKSEL_MASK);
+	/* Enable optional additional functional clock for IPU1 */
+	setbits_le32((*prcm)->cm1_abe_timer8_clkctrl,
+		     IPU1_CLKCTRL_CLKSEL_MASK);
+}
+
+/*
+ * Enable IPU2 clock domains, modules and
+ * do some additional special settings needed
+ */
+void enable_ipu2_clocks(void)
+{
+	if (!IS_ENABLED(CONFIG_DRA7XX) ||
+	    !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+		return;
+
+	u32 const clk_domains[] = {
+		(*prcm)->cm_ipu_clkstctrl,
+		(*prcm)->cm_ipu2_clkstctrl,
+		0
+	};
+
+	u32 const clk_modules_hw_auto_essential[] = {
+		(*prcm)->cm_ipu2_ipu2_clkctrl,
+		0
+	};
+
+	u32 const clk_modules_explicit_en_essential[] = {
+		(*prcm)->cm_l4per_gptimer3_clkctrl,
+		(*prcm)->cm_l4per_gptimer4_clkctrl,
+		(*prcm)->cm_l4per_gptimer9_clkctrl,
+		0
+	};
+	do_enable_ipu_clocks(clk_domains, clk_modules_hw_auto_essential,
+			     clk_modules_explicit_en_essential, 0);
+
+	/* Enable optional additional functional clock for IPU2 */
+	setbits_le32((*prcm)->cm_l4per_gptimer4_clkctrl,
+		     IPU1_CLKCTRL_CLKSEL_MASK);
+	/* Enable optional additional functional clock for IPU2 */
+	setbits_le32((*prcm)->cm_l4per_gptimer9_clkctrl,
+		     IPU1_CLKCTRL_CLKSEL_MASK);
+}
+
+/*
  * Enable essential clock domains, modules and
  * do some additional special settings needed
  */
@@ -478,12 +557,13 @@ void enable_basic_clocks(void)
 
 void enable_basic_uboot_clocks(void)
 {
-	u32 const clk_domains_essential[] = {
-#if defined(CONFIG_DRA7XX)
-		(*prcm)->cm_ipu_clkstctrl,
-#endif
-		0
-	};
+	u32 cm_ipu_clkstctrl = 0;
+
+	if (IS_ENABLED(CONFIG_DRA7XX) &&
+	    !IS_ENABLED(CONFIG_REMOTEPROC_TI_IPU))
+		cm_ipu_clkstctrl = (*prcm)->cm_ipu_clkstctrl;
+
+	u32 const clk_domains_essential[] = {cm_ipu_clkstctrl, 0};
 
 	u32 const clk_modules_hw_auto_essential[] = {
 		(*prcm)->cm_l3init_hsusbtll_clkctrl,
diff --git a/arch/arm/mach-omap2/omap5/prcm-regs.c b/arch/arm/mach-omap2/omap5/prcm-regs.c
index 28c4f4f7374..d7196a3156c 100644
--- a/arch/arm/mach-omap2/omap5/prcm-regs.c
+++ b/arch/arm/mach-omap2/omap5/prcm-regs.c
@@ -832,7 +832,10 @@ struct prcm_regs const dra7xx_prcm = {
 	/* cm IPU */
 	.cm_ipu_clkstctrl			= 0x4a005540,
 	.cm_ipu_i2c5_clkctrl			= 0x4a005578,
-
+	.cm_ipu1_clkstctrl			= 0x4a005500,
+	.cm_ipu1_ipu1_clkctrl			= 0x4a005520,
+	.cm_ipu2_clkstctrl			= 0x4a008900,
+	.cm_ipu2_ipu2_clkctrl			= 0x4a008920,
 	/* prm irqstatus regs */
 	.prm_irqstatus_mpu			= 0x4ae06010,
 	.prm_irqstatus_mpu_2			= 0x4ae06014,
@@ -1013,6 +1016,10 @@ struct prcm_regs const dra7xx_prcm = {
 	/*l3main1 edma*/
 	.cm_l3main1_tptc1_clkctrl               = 0x4a008778,
 	.cm_l3main1_tptc2_clkctrl               = 0x4a008780,
+
+	/* cm1.abe */
+	.cm1_abe_timer7_clkctrl = 0x4a005568,
+	.cm1_abe_timer8_clkctrl = 0x4a005570,
 };
 
 void clrset_spare_register(u8 spare_type, u32 clear_bits, u32 set_bits)