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authorJorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>2018-01-10 11:33:50 +0100
committerTom Rini <trini@konsulko.com>2018-01-15 16:29:02 -0500
commit4b684a6b82572654b7398d871aa138398c2b18c7 (patch)
tree66aaaaa9f44d7d26f6509caca78fe35d1f4c68e7 /arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
parent7c75f7f1b29eb53912b75472f4d8135c465f87f5 (diff)
db820c: add qualcomm dragonboard 820C support
This commit adds support for 96Boards Dragonboard820C. The board is based on APQ8086 Qualcomm Soc, complying with the 96Boards specification. Features - 4x Kyro CPU (64 bit) up to 2.15GHz - USB2.0 - USB3.0 - ISP - Qualcomm Hexagon DSP - SD 3.0 (UHS-I) - UFS 2.0 - Qualcomm Adreno 530 GPU - GPS - BT 4.2 - Wi-Fi 2.4GHz, 5GHz (802.11ac) - PCIe 2.0 - MIPI-CSI, MIPI-DSI - I2S U-Boot boots chained from LK (LK implements the fastboot protocol) in 64-bit mode. For detailed build instructions see readme.txt in the board directory. Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Diffstat (limited to 'arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h')
-rw-r--r--arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h29
1 files changed, 29 insertions, 0 deletions
diff --git a/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
new file mode 100644
index 00000000000..fb89de258de
--- /dev/null
+++ b/arch/arm/mach-snapdragon/include/mach/sysmap-apq8096.h
@@ -0,0 +1,29 @@
+/*
+ * Qualcomm APQ8096 sysmap
+ *
+ * (C) Copyright 2017 Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+#ifndef _MACH_SYSMAP_APQ8096_H
+#define _MACH_SYSMAP_APQ8096_H
+
+#define TLMM_BASE_ADDR (0x1010000)
+
+/* Strength (sdc1) */
+#define SDC1_HDRV_PULL_CTL_REG (TLMM_BASE_ADDR + 0x0012D000)
+
+/* Clocks: (from CLK_CTL_BASE) */
+#define GPLL0_STATUS (0x0000)
+#define APCS_GPLL_ENA_VOTE (0x52000)
+
+#define SDCC2_BCR (0x14000) /* block reset */
+#define SDCC2_APPS_CBCR (0x14004) /* branch control */
+#define SDCC2_AHB_CBCR (0x14008)
+#define SDCC2_CMD_RCGR (0x14010)
+#define SDCC2_CFG_RCGR (0x14014)
+#define SDCC2_M (0x14018)
+#define SDCC2_N (0x1401C)
+#define SDCC2_D (0x14020)
+
+#endif