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| author | Tom Rini <trini@konsulko.com> | 2020-01-08 15:23:49 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2020-01-08 15:23:49 -0500 |
| commit | ce022f2857714e19c6b31a023b8145782ecef5a5 (patch) | |
| tree | c7a3666314cdcb3a2d3ae2a88a579dbf4ebfc3e1 /arch/arm/mach-socfpga/clock_manager.c | |
| parent | 9af51fb3a505f895d64bd1f8a5967bfaa510add4 (diff) | |
| parent | 8097aee3abc3b773aceea01f756a38b34b274e1e (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
Diffstat (limited to 'arch/arm/mach-socfpga/clock_manager.c')
| -rw-r--r-- | arch/arm/mach-socfpga/clock_manager.c | 14 |
1 files changed, 7 insertions, 7 deletions
diff --git a/arch/arm/mach-socfpga/clock_manager.c b/arch/arm/mach-socfpga/clock_manager.c index 9f3c643df88..dbb10ecb681 100644 --- a/arch/arm/mach-socfpga/clock_manager.c +++ b/arch/arm/mach-socfpga/clock_manager.c @@ -10,18 +10,17 @@ DECLARE_GLOBAL_DATA_PTR; -static const struct socfpga_clock_manager *clock_manager_base = - (struct socfpga_clock_manager *)SOCFPGA_CLKMGR_ADDRESS; - void cm_wait_for_lock(u32 mask) { u32 inter_val; u32 retry = 0; do { #if defined(CONFIG_TARGET_SOCFPGA_GEN5) - inter_val = readl(&clock_manager_base->inter) & mask; + inter_val = readl(socfpga_get_clkmgr_addr() + + CLKMGR_INTER) & mask; #else - inter_val = readl(&clock_manager_base->stat) & mask; + inter_val = readl(socfpga_get_clkmgr_addr() + + CLKMGR_STAT) & mask; #endif /* Wait for stable lock */ if (inter_val == mask) @@ -36,8 +35,9 @@ void cm_wait_for_lock(u32 mask) /* function to poll in the fsm busy bit */ int cm_wait_for_fsm(void) { - return wait_for_bit_le32(&clock_manager_base->stat, - CLKMGR_STAT_BUSY, false, 20000, false); + return wait_for_bit_le32((const void *)(socfpga_get_clkmgr_addr() + + CLKMGR_STAT), CLKMGR_STAT_BUSY, false, 20000, + false); } int set_cpu_clk_info(void) |