diff options
| author | Tom Rini <trini@konsulko.com> | 2024-03-19 09:10:30 -0400 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2024-03-19 09:10:30 -0400 |
| commit | f048104999db28d49362201eaebfc91adb14f47c (patch) | |
| tree | d8a909e13b846bb4a443283a3d948a39bb835995 /arch/arm/mach-socfpga/include/mach/clock_manager.h | |
| parent | b145877c22b391a4872c875145a8f86f6ffebaba (diff) | |
| parent | 386fca68960994ece0d9da8a69a14495b5f1aedf (diff) | |
Merge tag 'u-boot-socfpga-next-20240319' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
- A new driver in the misc to register setting from device tree. This
also provides user a clean interface and all register settings are
centralized in one place, device tree.
- Enable Agilex5 platform for Intel product. Changes, modification and
new files are created for board, dts, configs and makefile to create
the base for Agilex5.
Build-tested on SoC64 boards, boot tested on some of them.
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/clock_manager.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/clock_manager.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/clock_manager.h b/arch/arm/mach-socfpga/include/mach/clock_manager.h index a8cb07a1c47..6c9d32b9dd8 100644 --- a/arch/arm/mach-socfpga/include/mach/clock_manager.h +++ b/arch/arm/mach-socfpga/include/mach/clock_manager.h @@ -1,6 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0+ */ /* - * Copyright (C) 2013-2017 Altera Corporation <www.altera.com> + * Copyright (C) 2013-2024 Altera Corporation <www.altera.com> */ #ifndef _CLOCK_MANAGER_H_ @@ -28,6 +28,8 @@ int cm_set_qspi_controller_clk_hz(u32 clk_hz); #include <asm/arch/clock_manager_s10.h> #elif defined(CONFIG_TARGET_SOCFPGA_AGILEX) #include <asm/arch/clock_manager_agilex.h> +#elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5) +#include <asm/arch/clock_manager_agilex5.h> #elif IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X) #include <asm/arch/clock_manager_n5x.h> #endif |