diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-08-03 18:24:41 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-08-08 22:20:49 +0800 |
| commit | 1e354de7fc36c5cf1f7e77c5dca4713100fbb503 (patch) | |
| tree | 2660cc7036772b739c487e0961f12991f05d3d36 /arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | |
| parent | 209d53eb1b486776dd1a7ad7f8611083fff7ad26 (diff) | |
ddr: altera: agilex: Get ACF from boot scratch register
The DDR data rate must be set correctly in the DDRIOCTRL
register according to the Actual Clock Frequency (ACF) value.
By enabling the reading of ACF value from bit 18 of the boot
scratch register during initialization, the DDR data rate is
able to be configured accurately.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach/system_manager_soc64.h')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/system_manager_soc64.h | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h index 8e12aeec011..0871cf949e5 100644 --- a/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/system_manager_soc64.h @@ -148,11 +148,14 @@ void populate_sysmgr_pinmux(void); * Bit[30] reserved for FSBL to update the DDR init progress * 1 - means in progress, 0 - haven't started / DDR is up running. * + * Bit[18] reserved for SDM to configure ACF * Bit[17:1] - Setting by Linux EDAC. * Bit[1](ECC_OCRAM), Bit[16](ECC_DDR0), Bit[17](ECC_DDR1) */ #define ALT_SYSMGR_SCRATCH_REG_8_DDR_DBE_MASK BIT(31) #define ALT_SYSMGR_SCRATCH_REG_8_DDR_PROGRESS_MASK BIT(30) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_MASK BIT(18) +#define SYSMGR_SCRATCH_REG_8_ACF_DDR_RATE_SHIFT 18 #define SYSMGR_SDMMC SYSMGR_SOC64_SDMMC |