diff options
| author | Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> | 2025-04-03 19:07:03 -0700 |
|---|---|---|
| committer | Tien Fong Chee <tien.fong.chee@intel.com> | 2025-04-22 11:47:39 +0800 |
| commit | cf5b58ef6ed577f07ad76ec5024060c84acef481 (patch) | |
| tree | 7609400e48ef5c37f2f61de7f99ea4980cd1c45a /arch/arm/mach-socfpga/include/mach | |
| parent | 9acad2b4c7214bb423a6221b67b0d7ea37edbdf7 (diff) | |
arm: socfpga: soc64: Enable F2S bridge reset support
Enable reset support for FPGA2SDRAM bridge for Stratix10, as well as
FPGA2SoC and SoC2FPGA bridges for all SoC64 families.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com>
Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/include/mach')
| -rw-r--r-- | arch/arm/mach-socfpga/include/mach/base_addr_soc64.h | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h index 65721098b2b..5ac868a281b 100644 --- a/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h +++ b/arch/arm/mach-socfpga/include/mach/base_addr_soc64.h @@ -51,6 +51,7 @@ #else #define SOCFPGA_FW_MPU_DDR_SCR_ADDRESS 0xf8020100 #endif +#define SOCFPGA_F2SDRAM_MGR_ADDRESS 0xf8024000 #define SOCFPGA_SMMU_ADDRESS 0xfa000000 #define SOCFPGA_MAILBOX_ADDRESS 0xffa30000 #define SOCFPGA_UART0_ADDRESS 0xffc02000 |