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authorTien Fong Chee <tien.fong.chee@intel.com>2024-09-18 16:43:02 +0800
committerTom Rini <trini@konsulko.com>2025-02-25 10:53:31 -0600
commit35638172f99a4974489a8ea85f4727382bcde22d (patch)
treed1f149128f874cd89d2d40dbeb1b9fc1231b32f5 /arch/arm/mach-socfpga/misc.c
parentcbb6b57d3edf4a14aea22558a16a694100665524 (diff)
arm: socfpga: agilex5: Add new driver model for system manager in Agilex5
Initial creation of new system manager driver. Add supports for the SOCFPGA System Manager Register block which aggregates different peripheral function into one area. On 64 bit ARM parts, the system manager only can be accessed during EL3 mode, this driver model provide user the high level access to system register and abstract user from low level access. The base address of system manager can be retrieved using DT framework through the System Manager driver. Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Boon Khai Ng <boon.khai.ng@altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
-rw-r--r--arch/arm/mach-socfpga/misc.c18
1 files changed, 14 insertions, 4 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 46f9c82bbb2..9d464307665 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -248,10 +248,6 @@ void socfpga_get_managers_addr(void)
if (ret)
hang();
- ret = socfpga_get_base_addr("altr,sys-mgr", &socfpga_sysmgr_base);
- if (ret)
- hang();
-
#ifdef CONFIG_TARGET_SOCFPGA_AGILEX
ret = socfpga_get_base_addr("intel,agilex-clkmgr",
&socfpga_clkmgr_base);
@@ -265,6 +261,20 @@ void socfpga_get_managers_addr(void)
hang();
}
+void socfpga_get_sys_mgr_addr(const char *compat)
+{
+ int ret;
+ struct udevice *sysmgr_dev;
+
+ ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev);
+ if (ret) {
+ printf("Altera system manager init failed: %d\n", ret);
+ hang();
+ } else {
+ socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev);
+ }
+}
+
phys_addr_t socfpga_get_rstmgr_addr(void)
{
return socfpga_rstmgr_base;