Merge tag 'u-boot-socfpga-next-20250808' of https://source.denx.de/u-boot/custodians/u-boot-socfpga

This pull request introduces initial U-Boot support for Agilex7 M-series, along
with several enhancements and cleanups across existing Agilex platforms. Key
changes include new board support, DDR driver additions, updated device trees,
and broader SoCFPGA SPL improvements.

Highlights:

- Agilex7 M-series bring-up:
  - Basic DT support and board initialization for Agilex7 M-series SoC and
    SoCDK.
  - New sdram_agilex7m DDR driver with UIBSSM mailbox support and HBM support.
  - Clock driver support for Agilex7 M-series.
  - New defconfig: socfpga_agilex7m_defconfig.
- Agilex and Agilex5 enhancements:
  - Improved SPL support: ASYNC interrupt enabling, system manager init
    refactor, and cold scratch register usage.
  - Updated firewall probing and watchdog support in SPL.
  - Cleaned up DDR code, added secure region support for ATF, and improved warm
    reset handling.
- Device Tree and config updates:
  - Migration to upstream Linux DT layout for Agilex platforms.
  - Consolidated socfpga_agilex_defconfig and removed deprecated configs.
  - Platform-specific environment variables for Distro Boot added.
- Driver fixes and cleanups:
  - dwc_eth_xgmac and clk-agilex cleanup and improvements.
  - Several coverity and style fixes.

Contributions in this PR are from Alif Zakuan Yuslaimi, Tingting Meng, and
Andrew Goodbody.  This patch set has been tested on Agilex 5 devkit, Agilex
devkit and Agilex7m devkit.

Passing all pipeline tests at SoCFPGA U-boot custodian
https://source.denx.de/u-boot/custodians/u-boot-socfpga/-/pipelines/27318

1 files changed, 17 insertions, 10 deletions

diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index 97e01140513..76747c2196a 100644
--- a/arch/arm/mach-socfpga/misc.c
+++ b/arch/arm/mach-socfpga/misc.c
@@ -11,6 +11,7 @@
 #include <hang.h>
 #include <watchdog.h>
 #include <fdtdec.h>
+#include <dm/ofnode.h>
 #include <linux/libfdt.h>
 #include <linux/printk.h>
 #include <miiphy.h>
@@ -222,8 +223,8 @@ static int do_bridge(struct cmd_tbl *cmdtp, int flag, int argc,
 
 U_BOOT_CMD(bridge, 3, 1, do_bridge,
 	   "SoCFPGA HPS FPGA bridge control",
-	   "enable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
-	   "bridge disable [mask] - Enable HPS-to-FPGA, FPGA-to-HPS, LWHPS-to-FPGA bridges\n"
+	   "enable [mask] - Enable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
+	   "bridge disable [mask] - Disable HPS-to-FPGA (Bit 0), LWHPS-to-FPGA (Bit 1), FPGA-to-HPS (Bit 2) bridges\n"
 	   ""
 );
 
@@ -260,13 +261,12 @@ void socfpga_get_managers_addr(void)
 	if (ret)
 		hang();
 
-	if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX))
-		ret = socfpga_get_base_addr("intel,agilex-clkmgr",
-					    &socfpga_clkmgr_base);
 	else if (IS_ENABLED(CONFIG_TARGET_SOCFPGA_N5X))
 		ret = socfpga_get_base_addr("intel,n5x-clkmgr",
 					    &socfpga_clkmgr_base);
-	else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
+	else if (!IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX) &&
+		 !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX7M) &&
+		 !IS_ENABLED(CONFIG_TARGET_SOCFPGA_AGILEX5))
 		ret = socfpga_get_base_addr("altr,clk-mgr",
 					    &socfpga_clkmgr_base);
 
@@ -274,17 +274,24 @@ void socfpga_get_managers_addr(void)
 		hang();
 }
 
-void socfpga_get_sys_mgr_addr(const char *compat)
+void socfpga_get_sys_mgr_addr(void)
 {
 	int ret;
-	struct udevice *sysmgr_dev;
+	struct udevice *dev;
+
+	ofnode node = ofnode_get_aliases_node("sysmgr");
+
+	if (!ofnode_valid(node)) {
+		printf("'sysmgr' alias not found in device tree\n");
+		hang();
+	}
 
-	ret = uclass_get_device_by_name(UCLASS_NOP, compat, &sysmgr_dev);
+	ret = uclass_get_device_by_ofnode(UCLASS_NOP, node, &dev);
 	if (ret) {
 		printf("Altera system manager init failed: %d\n", ret);
 		hang();
 	} else {
-		socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(sysmgr_dev);
+		socfpga_sysmgr_base = (phys_addr_t)dev_read_addr(dev);
 	}
 }