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| author | Tom Rini <trini@konsulko.com> | 2019-02-28 18:57:32 -0500 |
|---|---|---|
| committer | Tom Rini <trini@konsulko.com> | 2019-02-28 18:57:32 -0500 |
| commit | cfba74d0bef350d81241b059180bcc5a1e93bdfa (patch) | |
| tree | 125d54fbb44b958899ed63c9880f546d0f75dd5b /arch/arm/mach-socfpga/misc.c | |
| parent | 35b05146f6a4853554b18ddc196d3bfcab5dd734 (diff) | |
| parent | 4a9743f73c10a4b3801be3b662a892f61617256e (diff) | |
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- SoCFPGA cache/gpio fixes
Diffstat (limited to 'arch/arm/mach-socfpga/misc.c')
| -rw-r--r-- | arch/arm/mach-socfpga/misc.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c index e1adea143cf..fcf211d62bd 100644 --- a/arch/arm/mach-socfpga/misc.c +++ b/arch/arm/mach-socfpga/misc.c @@ -62,6 +62,9 @@ void v7_outer_cache_enable(void) /* Disable the L2 cache */ clrbits_le32(&pl310->pl310_ctrl, L2X0_CTRL_EN); + writel(0x111, &pl310->pl310_tag_latency_ctrl); + writel(0x121, &pl310->pl310_data_latency_ctrl); + /* enable BRESP, instruction and data prefetch, full line of zeroes */ setbits_le32(&pl310->pl310_aux_ctrl, L310_AUX_CTRL_DATA_PREFETCH_MASK | |