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authorAlif Zakuan Yuslaimi <alif.zakuan.yuslaimi@intel.com>2025-02-18 16:35:03 +0800
committerTom Rini <trini@konsulko.com>2025-02-25 10:54:00 -0600
commit034ebe3302200c033078455c5774ed739cd4f2ac (patch)
treeb0d34788eccb7b693097ff5c4f25d04d42708b4a /arch/arm/mach-socfpga/smc_api.c
parent19f20cfc49e385dd5ae5583ae68bd31f20de622c (diff)
arm: socfpga: smc: Add memory coherency support to mailbox command
As cache is enabled in U-Boot and disabled in ATF(BL31). We need to perform cache flush of buffers that are shared between U-Boot and ATF using secure monitor calls. Signed-off-by: Mahesh Rao <mahesh.rao@altera.com> Signed-off-by: Tien Fong Chee <tien.fong.chee@altera.com> Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Diffstat (limited to 'arch/arm/mach-socfpga/smc_api.c')
-rw-r--r--arch/arm/mach-socfpga/smc_api.c12
1 files changed, 10 insertions, 2 deletions
diff --git a/arch/arm/mach-socfpga/smc_api.c b/arch/arm/mach-socfpga/smc_api.c
index ebaa0b8fa17..b212a94b321 100644
--- a/arch/arm/mach-socfpga/smc_api.c
+++ b/arch/arm/mach-socfpga/smc_api.c
@@ -1,9 +1,11 @@
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2020 Intel Corporation <www.intel.com>
+ * Copyright (C) 2025 Altera Corporation <www.altera.com>
*
*/
+#include <cpu_func.h>
#include <asm/ptrace.h>
#include <asm/system.h>
#include <linux/errno.h>
@@ -40,10 +42,16 @@ int smc_send_mailbox(u32 cmd, u32 len, u32 *arg, u8 urgent, u32 *resp_buf_len,
args[2] = len;
args[3] = urgent;
args[4] = (u64)resp_buf;
- if (resp_buf_len)
+
+ if (arg && len > 0)
+ flush_dcache_range((uintptr_t)arg, (uintptr_t)arg + len);
+
+ if (resp_buf && resp_buf_len && *resp_buf_len > 0) {
args[5] = *resp_buf_len;
- else
+ flush_dcache_range((uintptr_t)resp_buf, (uintptr_t)resp_buf + *resp_buf_len);
+ } else {
args[5] = 0;
+ }
ret = invoke_smc(INTEL_SIP_SMC_MBOX_SEND_CMD, args, ARRAY_SIZE(args),
resp, ARRAY_SIZE(resp));